1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 #ifdef AARCH64 83 ARM_MAP_DRAM2, 84 #endif 85 #ifdef SPD_tspd 86 ARM_MAP_TSP_SEC_MEM, 87 #endif 88 #if TRUSTED_BOARD_BOOT 89 /* To access the Root of Trust Public Key registers. */ 90 MAP_DEVICE2, 91 #endif 92 #if ARM_BL31_IN_DRAM 93 ARM_MAP_BL31_SEC_DRAM, 94 #endif 95 #ifdef SPD_opteed 96 ARM_MAP_OPTEE_CORE_MEM, 97 ARM_OPTEE_PAGEABLE_LOAD_MEM, 98 #endif 99 {0} 100 }; 101 #endif 102 #ifdef IMAGE_BL2U 103 const mmap_region_t plat_arm_mmap[] = { 104 MAP_DEVICE0, 105 V2M_MAP_IOFPGA, 106 {0} 107 }; 108 #endif 109 #ifdef IMAGE_BL31 110 const mmap_region_t plat_arm_mmap[] = { 111 ARM_MAP_SHARED_RAM, 112 V2M_MAP_IOFPGA, 113 MAP_DEVICE0, 114 MAP_DEVICE1, 115 ARM_V2M_MAP_MEM_PROTECT, 116 {0} 117 }; 118 #endif 119 #ifdef IMAGE_BL32 120 const mmap_region_t plat_arm_mmap[] = { 121 #ifdef AARCH32 122 ARM_MAP_SHARED_RAM, 123 #endif 124 V2M_MAP_IOFPGA, 125 MAP_DEVICE0, 126 MAP_DEVICE1, 127 {0} 128 }; 129 #endif 130 131 ARM_CASSERT_MMAP 132 133 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 134 static const int fvp_cci400_map[] = { 135 PLAT_FVP_CCI400_CLUS0_SL_PORT, 136 PLAT_FVP_CCI400_CLUS1_SL_PORT, 137 }; 138 139 static const int fvp_cci5xx_map[] = { 140 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 141 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 142 }; 143 144 static unsigned int get_interconnect_master(void) 145 { 146 unsigned int master; 147 u_register_t mpidr; 148 149 mpidr = read_mpidr_el1(); 150 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 151 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 152 153 assert(master < FVP_CLUSTER_COUNT); 154 return master; 155 } 156 #endif 157 158 /******************************************************************************* 159 * A single boot loader stack is expected to work on both the Foundation FVP 160 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 161 * SYS_ID register provides a mechanism for detecting the differences between 162 * these platforms. This information is stored in a per-BL array to allow the 163 * code to take the correct path.Per BL platform configuration. 164 ******************************************************************************/ 165 void fvp_config_setup(void) 166 { 167 unsigned int rev, hbi, bld, arch, sys_id; 168 169 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 170 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 171 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 172 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 173 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 174 175 if (arch != ARCH_MODEL) { 176 ERROR("This firmware is for FVP models\n"); 177 panic(); 178 } 179 180 /* 181 * The build field in the SYS_ID tells which variant of the GIC 182 * memory is implemented by the model. 183 */ 184 switch (bld) { 185 case BLD_GIC_VE_MMAP: 186 ERROR("Legacy Versatile Express memory map for GIC peripheral" 187 " is not supported\n"); 188 panic(); 189 break; 190 case BLD_GIC_A53A57_MMAP: 191 break; 192 default: 193 ERROR("Unsupported board build %x\n", bld); 194 panic(); 195 } 196 197 /* 198 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 199 * for the Foundation FVP. 200 */ 201 switch (hbi) { 202 case HBI_FOUNDATION_FVP: 203 arm_config.flags = 0; 204 205 /* 206 * Check for supported revisions of Foundation FVP 207 * Allow future revisions to run but emit warning diagnostic 208 */ 209 switch (rev) { 210 case REV_FOUNDATION_FVP_V2_0: 211 case REV_FOUNDATION_FVP_V2_1: 212 case REV_FOUNDATION_FVP_v9_1: 213 case REV_FOUNDATION_FVP_v9_6: 214 break; 215 default: 216 WARN("Unrecognized Foundation FVP revision %x\n", rev); 217 break; 218 } 219 break; 220 case HBI_BASE_FVP: 221 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 222 223 /* 224 * Check for supported revisions 225 * Allow future revisions to run but emit warning diagnostic 226 */ 227 switch (rev) { 228 case REV_BASE_FVP_V0: 229 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 230 break; 231 case REV_BASE_FVP_REVC: 232 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 233 ARM_CONFIG_FVP_HAS_CCI5XX); 234 break; 235 default: 236 WARN("Unrecognized Base FVP revision %x\n", rev); 237 break; 238 } 239 break; 240 default: 241 ERROR("Unsupported board HBI number 0x%x\n", hbi); 242 panic(); 243 } 244 245 /* 246 * We assume that the presence of MT bit, and therefore shifted 247 * affinities, is uniform across the platform: either all CPUs, or no 248 * CPUs implement it. 249 */ 250 if (read_mpidr_el1() & MPIDR_MT_MASK) 251 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 252 } 253 254 255 void fvp_interconnect_init(void) 256 { 257 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 258 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 259 ERROR("Unrecognized CCN variant detected. Only CCN-502" 260 " is supported"); 261 panic(); 262 } 263 264 plat_arm_interconnect_init(); 265 #else 266 uintptr_t cci_base = 0; 267 const int *cci_map = 0; 268 unsigned int map_size = 0; 269 270 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 271 ARM_CONFIG_FVP_HAS_CCI5XX))) { 272 return; 273 } 274 275 /* Initialize the right interconnect */ 276 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 277 cci_base = PLAT_FVP_CCI5XX_BASE; 278 cci_map = fvp_cci5xx_map; 279 map_size = ARRAY_SIZE(fvp_cci5xx_map); 280 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 281 cci_base = PLAT_FVP_CCI400_BASE; 282 cci_map = fvp_cci400_map; 283 map_size = ARRAY_SIZE(fvp_cci400_map); 284 } 285 286 assert(cci_base); 287 assert(cci_map); 288 cci_init(cci_base, cci_map, map_size); 289 #endif 290 } 291 292 void fvp_interconnect_enable(void) 293 { 294 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 295 plat_arm_interconnect_enter_coherency(); 296 #else 297 unsigned int master; 298 299 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 300 ARM_CONFIG_FVP_HAS_CCI5XX)) { 301 master = get_interconnect_master(); 302 cci_enable_snoop_dvm_reqs(master); 303 } 304 #endif 305 } 306 307 void fvp_interconnect_disable(void) 308 { 309 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 310 plat_arm_interconnect_exit_coherency(); 311 #else 312 unsigned int master; 313 314 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 315 ARM_CONFIG_FVP_HAS_CCI5XX)) { 316 master = get_interconnect_master(); 317 cci_disable_snoop_dvm_reqs(master); 318 } 319 #endif 320 } 321