1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm_config.h> 32 #include <arm_def.h> 33 #include <ccn.h> 34 #include <debug.h> 35 #include <gicv2.h> 36 #include <mmio.h> 37 #include <plat_arm.h> 38 #include <v2m_def.h> 39 #include "../fvp_def.h" 40 41 /* Defines for GIC Driver build time selection */ 42 #define FVP_GICV2 1 43 #define FVP_GICV3 2 44 #define FVP_GICV3_LEGACY 3 45 46 /******************************************************************************* 47 * arm_config holds the characteristics of the differences between the three FVP 48 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 49 * at each boot stage by the primary before enabling the MMU (to allow 50 * interconnect configuration) & used thereafter. Each BL will have its own copy 51 * to allow independent operation. 52 ******************************************************************************/ 53 arm_config_t arm_config; 54 55 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 56 DEVICE0_SIZE, \ 57 MT_DEVICE | MT_RW | MT_SECURE) 58 59 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 60 DEVICE1_SIZE, \ 61 MT_DEVICE | MT_RW | MT_SECURE) 62 63 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 64 DEVICE2_SIZE, \ 65 MT_DEVICE | MT_RW | MT_SECURE) 66 67 68 /* 69 * Table of memory regions for various BL stages to map using the MMU. 70 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 71 * takes care of mapping it. 72 * 73 * The flash needs to be mapped as writable in order to erase the FIP's Table of 74 * Contents in case of unrecoverable error (see plat_error_handler()). 75 */ 76 #if IMAGE_BL1 77 const mmap_region_t plat_arm_mmap[] = { 78 ARM_MAP_SHARED_RAM, 79 V2M_MAP_FLASH0_RW, 80 V2M_MAP_IOFPGA, 81 MAP_DEVICE0, 82 MAP_DEVICE1, 83 MAP_DEVICE2, 84 #if TRUSTED_BOARD_BOOT 85 ARM_MAP_NS_DRAM1, 86 #endif 87 {0} 88 }; 89 #endif 90 #if IMAGE_BL2 91 const mmap_region_t plat_arm_mmap[] = { 92 ARM_MAP_SHARED_RAM, 93 V2M_MAP_FLASH0_RW, 94 V2M_MAP_IOFPGA, 95 MAP_DEVICE0, 96 MAP_DEVICE1, 97 MAP_DEVICE2, 98 ARM_MAP_NS_DRAM1, 99 ARM_MAP_TSP_SEC_MEM, 100 #if ARM_BL31_IN_DRAM 101 ARM_MAP_BL31_SEC_DRAM, 102 #endif 103 {0} 104 }; 105 #endif 106 #if IMAGE_BL2U 107 const mmap_region_t plat_arm_mmap[] = { 108 MAP_DEVICE0, 109 V2M_MAP_IOFPGA, 110 {0} 111 }; 112 #endif 113 #if IMAGE_BL31 114 const mmap_region_t plat_arm_mmap[] = { 115 ARM_MAP_SHARED_RAM, 116 V2M_MAP_IOFPGA, 117 MAP_DEVICE0, 118 MAP_DEVICE1, 119 {0} 120 }; 121 #endif 122 #if IMAGE_BL32 123 const mmap_region_t plat_arm_mmap[] = { 124 #ifdef AARCH32 125 ARM_MAP_SHARED_RAM, 126 #endif 127 V2M_MAP_IOFPGA, 128 MAP_DEVICE0, 129 MAP_DEVICE1, 130 {0} 131 }; 132 #endif 133 134 ARM_CASSERT_MMAP 135 136 137 /******************************************************************************* 138 * A single boot loader stack is expected to work on both the Foundation FVP 139 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 140 * SYS_ID register provides a mechanism for detecting the differences between 141 * these platforms. This information is stored in a per-BL array to allow the 142 * code to take the correct path.Per BL platform configuration. 143 ******************************************************************************/ 144 void fvp_config_setup(void) 145 { 146 unsigned int rev, hbi, bld, arch, sys_id; 147 148 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 149 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 150 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 151 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 152 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 153 154 if (arch != ARCH_MODEL) { 155 ERROR("This firmware is for FVP models\n"); 156 panic(); 157 } 158 159 /* 160 * The build field in the SYS_ID tells which variant of the GIC 161 * memory is implemented by the model. 162 */ 163 switch (bld) { 164 case BLD_GIC_VE_MMAP: 165 ERROR("Legacy Versatile Express memory map for GIC peripheral" 166 " is not supported\n"); 167 panic(); 168 break; 169 case BLD_GIC_A53A57_MMAP: 170 break; 171 default: 172 ERROR("Unsupported board build %x\n", bld); 173 panic(); 174 } 175 176 /* 177 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 178 * for the Foundation FVP. 179 */ 180 switch (hbi) { 181 case HBI_FOUNDATION_FVP: 182 arm_config.flags = 0; 183 184 /* 185 * Check for supported revisions of Foundation FVP 186 * Allow future revisions to run but emit warning diagnostic 187 */ 188 switch (rev) { 189 case REV_FOUNDATION_FVP_V2_0: 190 case REV_FOUNDATION_FVP_V2_1: 191 case REV_FOUNDATION_FVP_v9_1: 192 break; 193 default: 194 WARN("Unrecognized Foundation FVP revision %x\n", rev); 195 break; 196 } 197 break; 198 case HBI_BASE_FVP: 199 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 200 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 201 202 /* 203 * Check for supported revisions 204 * Allow future revisions to run but emit warning diagnostic 205 */ 206 switch (rev) { 207 case REV_BASE_FVP_V0: 208 break; 209 default: 210 WARN("Unrecognized Base FVP revision %x\n", rev); 211 break; 212 } 213 break; 214 default: 215 ERROR("Unsupported board HBI number 0x%x\n", hbi); 216 panic(); 217 } 218 } 219 220 221 void fvp_interconnect_init(void) 222 { 223 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) { 224 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 225 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 226 ERROR("Unrecognized CCN variant detected. Only CCN-502" 227 " is supported"); 228 panic(); 229 } 230 #endif 231 plat_arm_interconnect_init(); 232 } 233 } 234 235 void fvp_interconnect_enable(void) 236 { 237 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 238 plat_arm_interconnect_enter_coherency(); 239 } 240 241 void fvp_interconnect_disable(void) 242 { 243 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 244 plat_arm_interconnect_exit_coherency(); 245 } 246