1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <arm_spm_def.h> 10 #include <arm_xlat_tables.h> 11 #include <assert.h> 12 #include <cci.h> 13 #include <ccn.h> 14 #include <debug.h> 15 #include <gicv2.h> 16 #include <mmio.h> 17 #include <plat_arm.h> 18 #include <secure_partition.h> 19 #include <v2m_def.h> 20 #include "../fvp_def.h" 21 22 /* Defines for GIC Driver build time selection */ 23 #define FVP_GICV2 1 24 #define FVP_GICV3 2 25 #define FVP_GICV3_LEGACY 3 26 27 /******************************************************************************* 28 * arm_config holds the characteristics of the differences between the three FVP 29 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 30 * at each boot stage by the primary before enabling the MMU (to allow 31 * interconnect configuration) & used thereafter. Each BL will have its own copy 32 * to allow independent operation. 33 ******************************************************************************/ 34 arm_config_t arm_config; 35 36 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 37 DEVICE0_SIZE, \ 38 MT_DEVICE | MT_RW | MT_SECURE) 39 40 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 41 DEVICE1_SIZE, \ 42 MT_DEVICE | MT_RW | MT_SECURE) 43 44 /* 45 * Need to be mapped with write permissions in order to set a new non-volatile 46 * counter value. 47 */ 48 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 49 DEVICE2_SIZE, \ 50 MT_DEVICE | MT_RW | MT_SECURE) 51 52 53 /* 54 * Table of memory regions for various BL stages to map using the MMU. 55 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 56 * takes care of mapping it. 57 * 58 * The flash needs to be mapped as writable in order to erase the FIP's Table of 59 * Contents in case of unrecoverable error (see plat_error_handler()). 60 */ 61 #ifdef IMAGE_BL1 62 const mmap_region_t plat_arm_mmap[] = { 63 ARM_MAP_SHARED_RAM, 64 V2M_MAP_FLASH0_RW, 65 V2M_MAP_IOFPGA, 66 MAP_DEVICE0, 67 MAP_DEVICE1, 68 #if TRUSTED_BOARD_BOOT 69 /* To access the Root of Trust Public Key registers. */ 70 MAP_DEVICE2, 71 /* Map DRAM to authenticate NS_BL2U image. */ 72 ARM_MAP_NS_DRAM1, 73 #endif 74 {0} 75 }; 76 #endif 77 #ifdef IMAGE_BL2 78 const mmap_region_t plat_arm_mmap[] = { 79 ARM_MAP_SHARED_RAM, 80 V2M_MAP_FLASH0_RW, 81 V2M_MAP_IOFPGA, 82 MAP_DEVICE0, 83 MAP_DEVICE1, 84 ARM_MAP_NS_DRAM1, 85 #ifdef AARCH64 86 ARM_MAP_DRAM2, 87 #endif 88 #ifdef SPD_tspd 89 ARM_MAP_TSP_SEC_MEM, 90 #endif 91 #if TRUSTED_BOARD_BOOT 92 /* To access the Root of Trust Public Key registers. */ 93 MAP_DEVICE2, 94 #endif 95 #if ENABLE_SPM 96 ARM_SP_IMAGE_MMAP, 97 #endif 98 #if ARM_BL31_IN_DRAM 99 ARM_MAP_BL31_SEC_DRAM, 100 #endif 101 #ifdef SPD_opteed 102 ARM_MAP_OPTEE_CORE_MEM, 103 ARM_OPTEE_PAGEABLE_LOAD_MEM, 104 #endif 105 {0} 106 }; 107 #endif 108 #ifdef IMAGE_BL2U 109 const mmap_region_t plat_arm_mmap[] = { 110 MAP_DEVICE0, 111 V2M_MAP_IOFPGA, 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL31 116 const mmap_region_t plat_arm_mmap[] = { 117 ARM_MAP_SHARED_RAM, 118 ARM_MAP_EL3_TZC_DRAM, 119 V2M_MAP_IOFPGA, 120 MAP_DEVICE0, 121 MAP_DEVICE1, 122 ARM_V2M_MAP_MEM_PROTECT, 123 #if ENABLE_SPM 124 ARM_SPM_BUF_EL3_MMAP, 125 #endif 126 {0} 127 }; 128 129 #if ENABLE_SPM && defined(IMAGE_BL31) 130 const mmap_region_t plat_arm_secure_partition_mmap[] = { 131 V2M_MAP_IOFPGA_EL0, /* for the UART */ 132 MAP_REGION_FLAT(DEVICE0_BASE, \ 133 DEVICE0_SIZE, \ 134 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 135 ARM_SP_IMAGE_MMAP, 136 ARM_SP_IMAGE_NS_BUF_MMAP, 137 ARM_SP_IMAGE_RW_MMAP, 138 ARM_SPM_BUF_EL0_MMAP, 139 {0} 140 }; 141 #endif 142 #endif 143 #ifdef IMAGE_BL32 144 const mmap_region_t plat_arm_mmap[] = { 145 #ifdef AARCH32 146 ARM_MAP_SHARED_RAM, 147 #endif 148 V2M_MAP_IOFPGA, 149 MAP_DEVICE0, 150 MAP_DEVICE1, 151 {0} 152 }; 153 #endif 154 155 ARM_CASSERT_MMAP 156 157 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 158 static const int fvp_cci400_map[] = { 159 PLAT_FVP_CCI400_CLUS0_SL_PORT, 160 PLAT_FVP_CCI400_CLUS1_SL_PORT, 161 }; 162 163 static const int fvp_cci5xx_map[] = { 164 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 165 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 166 }; 167 168 static unsigned int get_interconnect_master(void) 169 { 170 unsigned int master; 171 u_register_t mpidr; 172 173 mpidr = read_mpidr_el1(); 174 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 175 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 176 177 assert(master < FVP_CLUSTER_COUNT); 178 return master; 179 } 180 #endif 181 182 #if ENABLE_SPM && defined(IMAGE_BL31) 183 /* 184 * Boot information passed to a secure partition during initialisation. Linear 185 * indices in MP information will be filled at runtime. 186 */ 187 static secure_partition_mp_info_t sp_mp_info[] = { 188 [0] = {0x80000000, 0}, 189 [1] = {0x80000001, 0}, 190 [2] = {0x80000002, 0}, 191 [3] = {0x80000003, 0}, 192 [4] = {0x80000100, 0}, 193 [5] = {0x80000101, 0}, 194 [6] = {0x80000102, 0}, 195 [7] = {0x80000103, 0}, 196 }; 197 198 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 199 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 200 .h.version = VERSION_1, 201 .h.size = sizeof(secure_partition_boot_info_t), 202 .h.attr = 0, 203 .sp_mem_base = ARM_SP_IMAGE_BASE, 204 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 205 .sp_image_base = ARM_SP_IMAGE_BASE, 206 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 207 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 208 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE, 209 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 210 .sp_image_size = ARM_SP_IMAGE_SIZE, 211 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 212 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 213 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE, 214 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 215 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 216 .num_cpus = PLATFORM_CORE_COUNT, 217 .mp_info = &sp_mp_info[0], 218 }; 219 220 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 221 { 222 return plat_arm_secure_partition_mmap; 223 } 224 225 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 226 void *cookie) 227 { 228 return &plat_arm_secure_partition_boot_info; 229 } 230 231 #endif 232 233 /******************************************************************************* 234 * A single boot loader stack is expected to work on both the Foundation FVP 235 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 236 * SYS_ID register provides a mechanism for detecting the differences between 237 * these platforms. This information is stored in a per-BL array to allow the 238 * code to take the correct path.Per BL platform configuration. 239 ******************************************************************************/ 240 void fvp_config_setup(void) 241 { 242 unsigned int rev, hbi, bld, arch, sys_id; 243 244 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 245 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 246 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 247 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 248 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 249 250 if (arch != ARCH_MODEL) { 251 ERROR("This firmware is for FVP models\n"); 252 panic(); 253 } 254 255 /* 256 * The build field in the SYS_ID tells which variant of the GIC 257 * memory is implemented by the model. 258 */ 259 switch (bld) { 260 case BLD_GIC_VE_MMAP: 261 ERROR("Legacy Versatile Express memory map for GIC peripheral" 262 " is not supported\n"); 263 panic(); 264 break; 265 case BLD_GIC_A53A57_MMAP: 266 break; 267 default: 268 ERROR("Unsupported board build %x\n", bld); 269 panic(); 270 } 271 272 /* 273 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 274 * for the Foundation FVP. 275 */ 276 switch (hbi) { 277 case HBI_FOUNDATION_FVP: 278 arm_config.flags = 0; 279 280 /* 281 * Check for supported revisions of Foundation FVP 282 * Allow future revisions to run but emit warning diagnostic 283 */ 284 switch (rev) { 285 case REV_FOUNDATION_FVP_V2_0: 286 case REV_FOUNDATION_FVP_V2_1: 287 case REV_FOUNDATION_FVP_v9_1: 288 case REV_FOUNDATION_FVP_v9_6: 289 break; 290 default: 291 WARN("Unrecognized Foundation FVP revision %x\n", rev); 292 break; 293 } 294 break; 295 case HBI_BASE_FVP: 296 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 297 298 /* 299 * Check for supported revisions 300 * Allow future revisions to run but emit warning diagnostic 301 */ 302 switch (rev) { 303 case REV_BASE_FVP_V0: 304 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 305 break; 306 case REV_BASE_FVP_REVC: 307 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 308 ARM_CONFIG_FVP_HAS_CCI5XX); 309 break; 310 default: 311 WARN("Unrecognized Base FVP revision %x\n", rev); 312 break; 313 } 314 break; 315 default: 316 ERROR("Unsupported board HBI number 0x%x\n", hbi); 317 panic(); 318 } 319 320 /* 321 * We assume that the presence of MT bit, and therefore shifted 322 * affinities, is uniform across the platform: either all CPUs, or no 323 * CPUs implement it. 324 */ 325 if (read_mpidr_el1() & MPIDR_MT_MASK) 326 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 327 } 328 329 330 void fvp_interconnect_init(void) 331 { 332 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 333 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 334 ERROR("Unrecognized CCN variant detected. Only CCN-502" 335 " is supported"); 336 panic(); 337 } 338 339 plat_arm_interconnect_init(); 340 #else 341 uintptr_t cci_base = 0; 342 const int *cci_map = 0; 343 unsigned int map_size = 0; 344 345 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 346 ARM_CONFIG_FVP_HAS_CCI5XX))) { 347 return; 348 } 349 350 /* Initialize the right interconnect */ 351 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 352 cci_base = PLAT_FVP_CCI5XX_BASE; 353 cci_map = fvp_cci5xx_map; 354 map_size = ARRAY_SIZE(fvp_cci5xx_map); 355 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 356 cci_base = PLAT_FVP_CCI400_BASE; 357 cci_map = fvp_cci400_map; 358 map_size = ARRAY_SIZE(fvp_cci400_map); 359 } 360 361 assert(cci_base); 362 assert(cci_map); 363 cci_init(cci_base, cci_map, map_size); 364 #endif 365 } 366 367 void fvp_interconnect_enable(void) 368 { 369 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 370 plat_arm_interconnect_enter_coherency(); 371 #else 372 unsigned int master; 373 374 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 375 ARM_CONFIG_FVP_HAS_CCI5XX)) { 376 master = get_interconnect_master(); 377 cci_enable_snoop_dvm_reqs(master); 378 } 379 #endif 380 } 381 382 void fvp_interconnect_disable(void) 383 { 384 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 385 plat_arm_interconnect_exit_coherency(); 386 #else 387 unsigned int master; 388 389 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 390 ARM_CONFIG_FVP_HAS_CCI5XX)) { 391 master = get_interconnect_master(); 392 cci_disable_snoop_dvm_reqs(master); 393 } 394 #endif 395 } 396