1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <arm_spm_def.h> 10 #include <arm_xlat_tables.h> 11 #include <assert.h> 12 #include <cci.h> 13 #include <ccn.h> 14 #include <debug.h> 15 #include <gicv2.h> 16 #include <mmio.h> 17 #include <plat_arm.h> 18 #include <platform.h> 19 #include <secure_partition.h> 20 #include <v2m_def.h> 21 #include "../fvp_def.h" 22 #include "fvp_private.h" 23 24 /* Defines for GIC Driver build time selection */ 25 #define FVP_GICV2 1 26 #define FVP_GICV3 2 27 28 /******************************************************************************* 29 * arm_config holds the characteristics of the differences between the three FVP 30 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 31 * at each boot stage by the primary before enabling the MMU (to allow 32 * interconnect configuration) & used thereafter. Each BL will have its own copy 33 * to allow independent operation. 34 ******************************************************************************/ 35 arm_config_t arm_config; 36 37 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 38 DEVICE0_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 42 DEVICE1_SIZE, \ 43 MT_DEVICE | MT_RW | MT_SECURE) 44 45 /* 46 * Need to be mapped with write permissions in order to set a new non-volatile 47 * counter value. 48 */ 49 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 50 DEVICE2_SIZE, \ 51 MT_DEVICE | MT_RW | MT_SECURE) 52 53 /* 54 * Table of memory regions for various BL stages to map using the MMU. 55 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 56 * takes care of mapping it. 57 * 58 * The flash needs to be mapped as writable in order to erase the FIP's Table of 59 * Contents in case of unrecoverable error (see plat_error_handler()). 60 */ 61 #ifdef IMAGE_BL1 62 const mmap_region_t plat_arm_mmap[] = { 63 ARM_MAP_SHARED_RAM, 64 V2M_MAP_FLASH0_RW, 65 V2M_MAP_IOFPGA, 66 MAP_DEVICE0, 67 MAP_DEVICE1, 68 #if TRUSTED_BOARD_BOOT 69 /* To access the Root of Trust Public Key registers. */ 70 MAP_DEVICE2, 71 /* Map DRAM to authenticate NS_BL2U image. */ 72 ARM_MAP_NS_DRAM1, 73 #endif 74 {0} 75 }; 76 #endif 77 #ifdef IMAGE_BL2 78 const mmap_region_t plat_arm_mmap[] = { 79 ARM_MAP_SHARED_RAM, 80 V2M_MAP_FLASH0_RW, 81 V2M_MAP_IOFPGA, 82 MAP_DEVICE0, 83 MAP_DEVICE1, 84 ARM_MAP_NS_DRAM1, 85 #ifdef AARCH64 86 ARM_MAP_DRAM2, 87 #endif 88 #ifdef SPD_tspd 89 ARM_MAP_TSP_SEC_MEM, 90 #endif 91 #if TRUSTED_BOARD_BOOT 92 /* To access the Root of Trust Public Key registers. */ 93 MAP_DEVICE2, 94 #if !BL2_AT_EL3 95 ARM_MAP_BL1_RW, 96 #endif 97 #endif /* TRUSTED_BOARD_BOOT */ 98 #if ENABLE_SPM 99 ARM_SP_IMAGE_MMAP, 100 #endif 101 #if ARM_BL31_IN_DRAM 102 ARM_MAP_BL31_SEC_DRAM, 103 #endif 104 #ifdef SPD_opteed 105 ARM_MAP_OPTEE_CORE_MEM, 106 ARM_OPTEE_PAGEABLE_LOAD_MEM, 107 #endif 108 {0} 109 }; 110 #endif 111 #ifdef IMAGE_BL2U 112 const mmap_region_t plat_arm_mmap[] = { 113 MAP_DEVICE0, 114 V2M_MAP_IOFPGA, 115 {0} 116 }; 117 #endif 118 #ifdef IMAGE_BL31 119 const mmap_region_t plat_arm_mmap[] = { 120 ARM_MAP_SHARED_RAM, 121 ARM_MAP_EL3_TZC_DRAM, 122 V2M_MAP_IOFPGA, 123 MAP_DEVICE0, 124 MAP_DEVICE1, 125 ARM_V2M_MAP_MEM_PROTECT, 126 #if ENABLE_SPM 127 ARM_SPM_BUF_EL3_MMAP, 128 #endif 129 {0} 130 }; 131 132 #if ENABLE_SPM && defined(IMAGE_BL31) 133 const mmap_region_t plat_arm_secure_partition_mmap[] = { 134 V2M_MAP_IOFPGA_EL0, /* for the UART */ 135 MAP_REGION_FLAT(DEVICE0_BASE, \ 136 DEVICE0_SIZE, \ 137 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 138 ARM_SP_IMAGE_MMAP, 139 ARM_SP_IMAGE_NS_BUF_MMAP, 140 ARM_SP_IMAGE_RW_MMAP, 141 ARM_SPM_BUF_EL0_MMAP, 142 {0} 143 }; 144 #endif 145 #endif 146 #ifdef IMAGE_BL32 147 const mmap_region_t plat_arm_mmap[] = { 148 #ifdef AARCH32 149 ARM_MAP_SHARED_RAM, 150 ARM_V2M_MAP_MEM_PROTECT, 151 #endif 152 V2M_MAP_IOFPGA, 153 MAP_DEVICE0, 154 MAP_DEVICE1, 155 {0} 156 }; 157 #endif 158 159 ARM_CASSERT_MMAP 160 161 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 162 static const int fvp_cci400_map[] = { 163 PLAT_FVP_CCI400_CLUS0_SL_PORT, 164 PLAT_FVP_CCI400_CLUS1_SL_PORT, 165 }; 166 167 static const int fvp_cci5xx_map[] = { 168 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 169 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 170 }; 171 172 static unsigned int get_interconnect_master(void) 173 { 174 unsigned int master; 175 u_register_t mpidr; 176 177 mpidr = read_mpidr_el1(); 178 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 179 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 180 181 assert(master < FVP_CLUSTER_COUNT); 182 return master; 183 } 184 #endif 185 186 #if ENABLE_SPM && defined(IMAGE_BL31) 187 /* 188 * Boot information passed to a secure partition during initialisation. Linear 189 * indices in MP information will be filled at runtime. 190 */ 191 static secure_partition_mp_info_t sp_mp_info[] = { 192 [0] = {0x80000000, 0}, 193 [1] = {0x80000001, 0}, 194 [2] = {0x80000002, 0}, 195 [3] = {0x80000003, 0}, 196 [4] = {0x80000100, 0}, 197 [5] = {0x80000101, 0}, 198 [6] = {0x80000102, 0}, 199 [7] = {0x80000103, 0}, 200 }; 201 202 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 203 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 204 .h.version = VERSION_1, 205 .h.size = sizeof(secure_partition_boot_info_t), 206 .h.attr = 0, 207 .sp_mem_base = ARM_SP_IMAGE_BASE, 208 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 209 .sp_image_base = ARM_SP_IMAGE_BASE, 210 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 211 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 212 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE, 213 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 214 .sp_image_size = ARM_SP_IMAGE_SIZE, 215 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 216 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 217 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE, 218 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 219 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 220 .num_cpus = PLATFORM_CORE_COUNT, 221 .mp_info = &sp_mp_info[0], 222 }; 223 224 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 225 { 226 return plat_arm_secure_partition_mmap; 227 } 228 229 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 230 void *cookie) 231 { 232 return &plat_arm_secure_partition_boot_info; 233 } 234 235 #endif 236 237 /******************************************************************************* 238 * A single boot loader stack is expected to work on both the Foundation FVP 239 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 240 * SYS_ID register provides a mechanism for detecting the differences between 241 * these platforms. This information is stored in a per-BL array to allow the 242 * code to take the correct path.Per BL platform configuration. 243 ******************************************************************************/ 244 void __init fvp_config_setup(void) 245 { 246 unsigned int rev, hbi, bld, arch, sys_id; 247 248 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 249 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 250 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 251 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 252 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 253 254 if (arch != ARCH_MODEL) { 255 ERROR("This firmware is for FVP models\n"); 256 panic(); 257 } 258 259 /* 260 * The build field in the SYS_ID tells which variant of the GIC 261 * memory is implemented by the model. 262 */ 263 switch (bld) { 264 case BLD_GIC_VE_MMAP: 265 ERROR("Legacy Versatile Express memory map for GIC peripheral" 266 " is not supported\n"); 267 panic(); 268 break; 269 case BLD_GIC_A53A57_MMAP: 270 break; 271 default: 272 ERROR("Unsupported board build %x\n", bld); 273 panic(); 274 } 275 276 /* 277 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 278 * for the Foundation FVP. 279 */ 280 switch (hbi) { 281 case HBI_FOUNDATION_FVP: 282 arm_config.flags = 0; 283 284 /* 285 * Check for supported revisions of Foundation FVP 286 * Allow future revisions to run but emit warning diagnostic 287 */ 288 switch (rev) { 289 case REV_FOUNDATION_FVP_V2_0: 290 case REV_FOUNDATION_FVP_V2_1: 291 case REV_FOUNDATION_FVP_v9_1: 292 case REV_FOUNDATION_FVP_v9_6: 293 break; 294 default: 295 WARN("Unrecognized Foundation FVP revision %x\n", rev); 296 break; 297 } 298 break; 299 case HBI_BASE_FVP: 300 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 301 302 /* 303 * Check for supported revisions 304 * Allow future revisions to run but emit warning diagnostic 305 */ 306 switch (rev) { 307 case REV_BASE_FVP_V0: 308 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 309 break; 310 case REV_BASE_FVP_REVC: 311 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 312 ARM_CONFIG_FVP_HAS_CCI5XX); 313 break; 314 default: 315 WARN("Unrecognized Base FVP revision %x\n", rev); 316 break; 317 } 318 break; 319 default: 320 ERROR("Unsupported board HBI number 0x%x\n", hbi); 321 panic(); 322 } 323 324 /* 325 * We assume that the presence of MT bit, and therefore shifted 326 * affinities, is uniform across the platform: either all CPUs, or no 327 * CPUs implement it. 328 */ 329 if (read_mpidr_el1() & MPIDR_MT_MASK) 330 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 331 } 332 333 334 void __init fvp_interconnect_init(void) 335 { 336 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 337 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 338 ERROR("Unrecognized CCN variant detected. Only CCN-502" 339 " is supported"); 340 panic(); 341 } 342 343 plat_arm_interconnect_init(); 344 #else 345 uintptr_t cci_base = 0; 346 const int *cci_map = 0; 347 unsigned int map_size = 0; 348 349 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 350 ARM_CONFIG_FVP_HAS_CCI5XX))) { 351 return; 352 } 353 354 /* Initialize the right interconnect */ 355 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 356 cci_base = PLAT_FVP_CCI5XX_BASE; 357 cci_map = fvp_cci5xx_map; 358 map_size = ARRAY_SIZE(fvp_cci5xx_map); 359 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 360 cci_base = PLAT_FVP_CCI400_BASE; 361 cci_map = fvp_cci400_map; 362 map_size = ARRAY_SIZE(fvp_cci400_map); 363 } 364 365 assert(cci_base); 366 assert(cci_map); 367 cci_init(cci_base, cci_map, map_size); 368 #endif 369 } 370 371 void fvp_interconnect_enable(void) 372 { 373 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 374 plat_arm_interconnect_enter_coherency(); 375 #else 376 unsigned int master; 377 378 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 379 ARM_CONFIG_FVP_HAS_CCI5XX)) { 380 master = get_interconnect_master(); 381 cci_enable_snoop_dvm_reqs(master); 382 } 383 #endif 384 } 385 386 void fvp_interconnect_disable(void) 387 { 388 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 389 plat_arm_interconnect_exit_coherency(); 390 #else 391 unsigned int master; 392 393 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 394 ARM_CONFIG_FVP_HAS_CCI5XX)) { 395 master = get_interconnect_master(); 396 cci_disable_snoop_dvm_reqs(master); 397 } 398 #endif 399 } 400 401 #if TRUSTED_BOARD_BOOT 402 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 403 { 404 assert(heap_addr != NULL); 405 assert(heap_size != NULL); 406 407 return arm_get_mbedtls_heap(heap_addr, heap_size); 408 } 409 #endif 410