1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <platform_def.h> 19 #include <services/arm_arch_svc.h> 20 #if SPM_MM 21 #include <services/spm_mm_partition.h> 22 #endif 23 24 #include <plat/arm/common/arm_config.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 28 #include "fvp_private.h" 29 30 /* Defines for GIC Driver build time selection */ 31 #define FVP_GICV2 1 32 #define FVP_GICV3 2 33 34 /******************************************************************************* 35 * arm_config holds the characteristics of the differences between the three FVP 36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 37 * at each boot stage by the primary before enabling the MMU (to allow 38 * interconnect configuration) & used thereafter. Each BL will have its own copy 39 * to allow independent operation. 40 ******************************************************************************/ 41 arm_config_t arm_config; 42 43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 44 DEVICE0_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 48 DEVICE1_SIZE, \ 49 MT_DEVICE | MT_RW | MT_SECURE) 50 51 #if FVP_GICR_REGION_PROTECTION 52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \ 53 BASE_GICD_SIZE, \ 54 MT_DEVICE | MT_RW | MT_SECURE) 55 56 /* Map all core's redistributor memory as read-only. After boots up, 57 * per-core map its redistributor memory as read-write */ 58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \ 59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\ 60 MT_DEVICE | MT_RO | MT_SECURE) 61 #endif /* FVP_GICR_REGION_PROTECTION */ 62 63 /* 64 * Need to be mapped with write permissions in order to set a new non-volatile 65 * counter value. 66 */ 67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 68 DEVICE2_SIZE, \ 69 MT_DEVICE | MT_RW | MT_SECURE) 70 71 /* 72 * Table of memory regions for various BL stages to map using the MMU. 73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 74 * of mapping it. 75 */ 76 #ifdef IMAGE_BL1 77 const mmap_region_t plat_arm_mmap[] = { 78 ARM_MAP_SHARED_RAM, 79 V2M_MAP_FLASH0_RO, 80 V2M_MAP_IOFPGA, 81 MAP_DEVICE0, 82 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 83 MAP_DEVICE1, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 /* Map DRAM to authenticate NS_BL2U image. */ 89 ARM_MAP_NS_DRAM1, 90 #endif 91 {0} 92 }; 93 #endif 94 #ifdef IMAGE_BL2 95 const mmap_region_t plat_arm_mmap[] = { 96 ARM_MAP_SHARED_RAM, 97 V2M_MAP_FLASH0_RW, 98 V2M_MAP_IOFPGA, 99 MAP_DEVICE0, 100 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 101 MAP_DEVICE1, 102 #endif 103 ARM_MAP_NS_DRAM1, 104 #ifdef __aarch64__ 105 ARM_MAP_DRAM2, 106 #endif 107 #if defined(SPD_spmd) 108 ARM_MAP_TRUSTED_DRAM, 109 #endif 110 #if ENABLE_RME 111 ARM_MAP_RMM_DRAM, 112 ARM_MAP_GPT_L1_DRAM, 113 #endif /* ENABLE_RME */ 114 #ifdef SPD_tspd 115 ARM_MAP_TSP_SEC_MEM, 116 #endif 117 #if TRUSTED_BOARD_BOOT 118 /* To access the Root of Trust Public Key registers. */ 119 MAP_DEVICE2, 120 #endif /* TRUSTED_BOARD_BOOT */ 121 122 #if CRYPTO_SUPPORT && !BL2_AT_EL3 123 /* 124 * To access shared the Mbed TLS heap while booting the 125 * system with Crypto support 126 */ 127 ARM_MAP_BL1_RW, 128 #endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */ 129 #if SPM_MM 130 ARM_SP_IMAGE_MMAP, 131 #endif 132 #if ARM_BL31_IN_DRAM 133 ARM_MAP_BL31_SEC_DRAM, 134 #endif 135 #ifdef SPD_opteed 136 ARM_MAP_OPTEE_CORE_MEM, 137 ARM_OPTEE_PAGEABLE_LOAD_MEM, 138 #endif 139 {0} 140 }; 141 #endif 142 #ifdef IMAGE_BL2U 143 const mmap_region_t plat_arm_mmap[] = { 144 MAP_DEVICE0, 145 V2M_MAP_IOFPGA, 146 {0} 147 }; 148 #endif 149 #ifdef IMAGE_BL31 150 const mmap_region_t plat_arm_mmap[] = { 151 ARM_MAP_SHARED_RAM, 152 #if USE_DEBUGFS 153 /* Required by devfip, can be removed if devfip is not used */ 154 V2M_MAP_FLASH0_RW, 155 #endif /* USE_DEBUGFS */ 156 ARM_MAP_EL3_TZC_DRAM, 157 V2M_MAP_IOFPGA, 158 MAP_DEVICE0, 159 #if FVP_GICR_REGION_PROTECTION 160 MAP_GICD_MEM, 161 MAP_GICR_MEM, 162 #else 163 MAP_DEVICE1, 164 #endif /* FVP_GICR_REGION_PROTECTION */ 165 ARM_V2M_MAP_MEM_PROTECT, 166 #if SPM_MM 167 ARM_SPM_BUF_EL3_MMAP, 168 #endif 169 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 170 ARM_DTB_DRAM_NS, 171 #if ENABLE_RME 172 ARM_MAP_GPT_L1_DRAM, 173 #endif 174 {0} 175 }; 176 177 #if defined(IMAGE_BL31) && SPM_MM 178 const mmap_region_t plat_arm_secure_partition_mmap[] = { 179 V2M_MAP_IOFPGA_EL0, /* for the UART */ 180 MAP_REGION_FLAT(DEVICE0_BASE, \ 181 DEVICE0_SIZE, \ 182 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 183 ARM_SP_IMAGE_MMAP, 184 ARM_SP_IMAGE_NS_BUF_MMAP, 185 ARM_SP_IMAGE_RW_MMAP, 186 ARM_SPM_BUF_EL0_MMAP, 187 {0} 188 }; 189 #endif 190 #endif 191 #ifdef IMAGE_BL32 192 const mmap_region_t plat_arm_mmap[] = { 193 #ifndef __aarch64__ 194 ARM_MAP_SHARED_RAM, 195 ARM_V2M_MAP_MEM_PROTECT, 196 #endif 197 V2M_MAP_IOFPGA, 198 MAP_DEVICE0, 199 MAP_DEVICE1, 200 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 201 ARM_DTB_DRAM_NS, 202 {0} 203 }; 204 #endif 205 206 #ifdef IMAGE_RMM 207 const mmap_region_t plat_arm_mmap[] = { 208 V2M_MAP_IOFPGA, 209 MAP_DEVICE0, 210 MAP_DEVICE1, 211 {0} 212 }; 213 #endif 214 215 ARM_CASSERT_MMAP 216 217 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 218 static const int fvp_cci400_map[] = { 219 PLAT_FVP_CCI400_CLUS0_SL_PORT, 220 PLAT_FVP_CCI400_CLUS1_SL_PORT, 221 }; 222 223 static const int fvp_cci5xx_map[] = { 224 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 225 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 226 }; 227 228 static unsigned int get_interconnect_master(void) 229 { 230 unsigned int master; 231 u_register_t mpidr; 232 233 mpidr = read_mpidr_el1(); 234 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 235 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 236 237 assert(master < FVP_CLUSTER_COUNT); 238 return master; 239 } 240 #endif 241 242 #if defined(IMAGE_BL31) && SPM_MM 243 /* 244 * Boot information passed to a secure partition during initialisation. Linear 245 * indices in MP information will be filled at runtime. 246 */ 247 static spm_mm_mp_info_t sp_mp_info[] = { 248 [0] = {0x80000000, 0}, 249 [1] = {0x80000001, 0}, 250 [2] = {0x80000002, 0}, 251 [3] = {0x80000003, 0}, 252 [4] = {0x80000100, 0}, 253 [5] = {0x80000101, 0}, 254 [6] = {0x80000102, 0}, 255 [7] = {0x80000103, 0}, 256 }; 257 258 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 259 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 260 .h.version = VERSION_1, 261 .h.size = sizeof(spm_mm_boot_info_t), 262 .h.attr = 0, 263 .sp_mem_base = ARM_SP_IMAGE_BASE, 264 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 265 .sp_image_base = ARM_SP_IMAGE_BASE, 266 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 267 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 268 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 269 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 270 .sp_image_size = ARM_SP_IMAGE_SIZE, 271 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 272 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 273 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 274 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 275 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 276 .num_cpus = PLATFORM_CORE_COUNT, 277 .mp_info = &sp_mp_info[0], 278 }; 279 280 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 281 { 282 return plat_arm_secure_partition_mmap; 283 } 284 285 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 286 void *cookie) 287 { 288 return &plat_arm_secure_partition_boot_info; 289 } 290 #endif 291 292 /******************************************************************************* 293 * A single boot loader stack is expected to work on both the Foundation FVP 294 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 295 * SYS_ID register provides a mechanism for detecting the differences between 296 * these platforms. This information is stored in a per-BL array to allow the 297 * code to take the correct path.Per BL platform configuration. 298 ******************************************************************************/ 299 void __init fvp_config_setup(void) 300 { 301 unsigned int rev, hbi, bld, arch, sys_id; 302 303 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 304 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 305 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 306 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 307 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 308 309 if (arch != ARCH_MODEL) { 310 ERROR("This firmware is for FVP models\n"); 311 panic(); 312 } 313 314 /* 315 * The build field in the SYS_ID tells which variant of the GIC 316 * memory is implemented by the model. 317 */ 318 switch (bld) { 319 case BLD_GIC_VE_MMAP: 320 ERROR("Legacy Versatile Express memory map for GIC peripheral" 321 " is not supported\n"); 322 panic(); 323 break; 324 case BLD_GIC_A53A57_MMAP: 325 break; 326 default: 327 ERROR("Unsupported board build %x\n", bld); 328 panic(); 329 } 330 331 /* 332 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 333 * for the Foundation FVP. 334 */ 335 switch (hbi) { 336 case HBI_FOUNDATION_FVP: 337 arm_config.flags = 0; 338 339 /* 340 * Check for supported revisions of Foundation FVP 341 * Allow future revisions to run but emit warning diagnostic 342 */ 343 switch (rev) { 344 case REV_FOUNDATION_FVP_V2_0: 345 case REV_FOUNDATION_FVP_V2_1: 346 case REV_FOUNDATION_FVP_v9_1: 347 case REV_FOUNDATION_FVP_v9_6: 348 break; 349 default: 350 WARN("Unrecognized Foundation FVP revision %x\n", rev); 351 break; 352 } 353 break; 354 case HBI_BASE_FVP: 355 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 356 357 /* 358 * Check for supported revisions 359 * Allow future revisions to run but emit warning diagnostic 360 */ 361 switch (rev) { 362 case REV_BASE_FVP_V0: 363 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 364 break; 365 case REV_BASE_FVP_REVC: 366 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 367 ARM_CONFIG_FVP_HAS_CCI5XX); 368 break; 369 default: 370 WARN("Unrecognized Base FVP revision %x\n", rev); 371 break; 372 } 373 break; 374 default: 375 ERROR("Unsupported board HBI number 0x%x\n", hbi); 376 panic(); 377 } 378 379 /* 380 * We assume that the presence of MT bit, and therefore shifted 381 * affinities, is uniform across the platform: either all CPUs, or no 382 * CPUs implement it. 383 */ 384 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 385 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 386 } 387 388 389 void __init fvp_interconnect_init(void) 390 { 391 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 392 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 393 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 394 panic(); 395 } 396 397 plat_arm_interconnect_init(); 398 #else 399 uintptr_t cci_base = 0U; 400 const int *cci_map = NULL; 401 unsigned int map_size = 0U; 402 403 /* Initialize the right interconnect */ 404 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 405 cci_base = PLAT_FVP_CCI5XX_BASE; 406 cci_map = fvp_cci5xx_map; 407 map_size = ARRAY_SIZE(fvp_cci5xx_map); 408 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 409 cci_base = PLAT_FVP_CCI400_BASE; 410 cci_map = fvp_cci400_map; 411 map_size = ARRAY_SIZE(fvp_cci400_map); 412 } else { 413 return; 414 } 415 416 assert(cci_base != 0U); 417 assert(cci_map != NULL); 418 cci_init(cci_base, cci_map, map_size); 419 #endif 420 } 421 422 void fvp_interconnect_enable(void) 423 { 424 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 425 plat_arm_interconnect_enter_coherency(); 426 #else 427 unsigned int master; 428 429 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 430 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 431 master = get_interconnect_master(); 432 cci_enable_snoop_dvm_reqs(master); 433 } 434 #endif 435 } 436 437 void fvp_interconnect_disable(void) 438 { 439 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 440 plat_arm_interconnect_exit_coherency(); 441 #else 442 unsigned int master; 443 444 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 445 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 446 master = get_interconnect_master(); 447 cci_disable_snoop_dvm_reqs(master); 448 } 449 #endif 450 } 451 452 #if CRYPTO_SUPPORT 453 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 454 { 455 assert(heap_addr != NULL); 456 assert(heap_size != NULL); 457 458 return arm_get_mbedtls_heap(heap_addr, heap_size); 459 } 460 #endif /* CRYPTO_SUPPORT */ 461 462 void fvp_timer_init(void) 463 { 464 #if USE_SP804_TIMER 465 /* Enable the clock override for SP804 timer 0, which means that no 466 * clock dividers are applied and the raw (35MHz) clock will be used. 467 */ 468 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 469 470 /* Initialize delay timer driver using SP804 dual timer 0 */ 471 sp804_timer_init(V2M_SP804_TIMER0_BASE, 472 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 473 #else 474 generic_delay_timer_init(); 475 476 /* Enable System level generic timer */ 477 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 478 CNTCR_FCREQ(0U) | CNTCR_EN); 479 #endif /* USE_SP804_TIMER */ 480 } 481 482 /***************************************************************************** 483 * plat_is_smccc_feature_available() - This function checks whether SMCCC 484 * feature is availabile for platform. 485 * @fid: SMCCC function id 486 * 487 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 488 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 489 *****************************************************************************/ 490 int32_t plat_is_smccc_feature_available(u_register_t fid) 491 { 492 switch (fid) { 493 case SMCCC_ARCH_SOC_ID: 494 return SMC_ARCH_CALL_SUCCESS; 495 default: 496 return SMC_ARCH_CALL_NOT_SUPPORTED; 497 } 498 } 499 500 /* Get SOC version */ 501 int32_t plat_get_soc_version(void) 502 { 503 return (int32_t) 504 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 505 ARM_SOC_IDENTIFICATION_CODE) | 506 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 507 } 508 509 /* Get SOC revision */ 510 int32_t plat_get_soc_revision(void) 511 { 512 unsigned int sys_id; 513 514 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 515 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 516 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 517 } 518