1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 #include <services/spm_mm_partition.h> 22 23 #include "fvp_private.h" 24 25 /* Defines for GIC Driver build time selection */ 26 #define FVP_GICV2 1 27 #define FVP_GICV3 2 28 29 /******************************************************************************* 30 * arm_config holds the characteristics of the differences between the three FVP 31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 32 * at each boot stage by the primary before enabling the MMU (to allow 33 * interconnect configuration) & used thereafter. Each BL will have its own copy 34 * to allow independent operation. 35 ******************************************************************************/ 36 arm_config_t arm_config; 37 38 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 39 DEVICE0_SIZE, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 43 DEVICE1_SIZE, \ 44 MT_DEVICE | MT_RW | MT_SECURE) 45 46 /* 47 * Need to be mapped with write permissions in order to set a new non-volatile 48 * counter value. 49 */ 50 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 51 DEVICE2_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE) 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 57 * of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef __aarch64__ 87 ARM_MAP_DRAM2, 88 #endif 89 #if defined(SPD_spmd) 90 ARM_MAP_TRUSTED_DRAM, 91 #endif 92 #ifdef SPD_tspd 93 ARM_MAP_TSP_SEC_MEM, 94 #endif 95 #if TRUSTED_BOARD_BOOT 96 /* To access the Root of Trust Public Key registers. */ 97 MAP_DEVICE2, 98 #if !BL2_AT_EL3 99 ARM_MAP_BL1_RW, 100 #endif 101 #endif /* TRUSTED_BOARD_BOOT */ 102 #if SPM_MM 103 ARM_SP_IMAGE_MMAP, 104 #endif 105 #if ARM_BL31_IN_DRAM 106 ARM_MAP_BL31_SEC_DRAM, 107 #endif 108 #ifdef SPD_opteed 109 ARM_MAP_OPTEE_CORE_MEM, 110 ARM_OPTEE_PAGEABLE_LOAD_MEM, 111 #endif 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL2U 116 const mmap_region_t plat_arm_mmap[] = { 117 MAP_DEVICE0, 118 V2M_MAP_IOFPGA, 119 {0} 120 }; 121 #endif 122 #ifdef IMAGE_BL31 123 const mmap_region_t plat_arm_mmap[] = { 124 ARM_MAP_SHARED_RAM, 125 #if USE_DEBUGFS 126 /* Required by devfip, can be removed if devfip is not used */ 127 V2M_MAP_FLASH0_RW, 128 #endif /* USE_DEBUGFS */ 129 ARM_MAP_EL3_TZC_DRAM, 130 V2M_MAP_IOFPGA, 131 MAP_DEVICE0, 132 MAP_DEVICE1, 133 ARM_V2M_MAP_MEM_PROTECT, 134 #if SPM_MM 135 ARM_SPM_BUF_EL3_MMAP, 136 #endif 137 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 138 ARM_DTB_DRAM_NS, 139 {0} 140 }; 141 142 #if defined(IMAGE_BL31) && SPM_MM 143 const mmap_region_t plat_arm_secure_partition_mmap[] = { 144 V2M_MAP_IOFPGA_EL0, /* for the UART */ 145 MAP_REGION_FLAT(DEVICE0_BASE, \ 146 DEVICE0_SIZE, \ 147 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 148 ARM_SP_IMAGE_MMAP, 149 ARM_SP_IMAGE_NS_BUF_MMAP, 150 ARM_SP_IMAGE_RW_MMAP, 151 ARM_SPM_BUF_EL0_MMAP, 152 {0} 153 }; 154 #endif 155 #endif 156 #ifdef IMAGE_BL32 157 const mmap_region_t plat_arm_mmap[] = { 158 #ifndef __aarch64__ 159 ARM_MAP_SHARED_RAM, 160 ARM_V2M_MAP_MEM_PROTECT, 161 #endif 162 V2M_MAP_IOFPGA, 163 MAP_DEVICE0, 164 MAP_DEVICE1, 165 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */ 166 ARM_DTB_DRAM_NS, 167 {0} 168 }; 169 #endif 170 171 ARM_CASSERT_MMAP 172 173 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 174 static const int fvp_cci400_map[] = { 175 PLAT_FVP_CCI400_CLUS0_SL_PORT, 176 PLAT_FVP_CCI400_CLUS1_SL_PORT, 177 }; 178 179 static const int fvp_cci5xx_map[] = { 180 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 181 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 182 }; 183 184 static unsigned int get_interconnect_master(void) 185 { 186 unsigned int master; 187 u_register_t mpidr; 188 189 mpidr = read_mpidr_el1(); 190 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 191 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 192 193 assert(master < FVP_CLUSTER_COUNT); 194 return master; 195 } 196 #endif 197 198 #if defined(IMAGE_BL31) && SPM_MM 199 /* 200 * Boot information passed to a secure partition during initialisation. Linear 201 * indices in MP information will be filled at runtime. 202 */ 203 static spm_mm_mp_info_t sp_mp_info[] = { 204 [0] = {0x80000000, 0}, 205 [1] = {0x80000001, 0}, 206 [2] = {0x80000002, 0}, 207 [3] = {0x80000003, 0}, 208 [4] = {0x80000100, 0}, 209 [5] = {0x80000101, 0}, 210 [6] = {0x80000102, 0}, 211 [7] = {0x80000103, 0}, 212 }; 213 214 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 215 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 216 .h.version = VERSION_1, 217 .h.size = sizeof(spm_mm_boot_info_t), 218 .h.attr = 0, 219 .sp_mem_base = ARM_SP_IMAGE_BASE, 220 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 221 .sp_image_base = ARM_SP_IMAGE_BASE, 222 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 223 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 224 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 225 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 226 .sp_image_size = ARM_SP_IMAGE_SIZE, 227 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 228 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 229 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 230 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 231 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 232 .num_cpus = PLATFORM_CORE_COUNT, 233 .mp_info = &sp_mp_info[0], 234 }; 235 236 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 237 { 238 return plat_arm_secure_partition_mmap; 239 } 240 241 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 242 void *cookie) 243 { 244 return &plat_arm_secure_partition_boot_info; 245 } 246 #endif 247 248 /******************************************************************************* 249 * A single boot loader stack is expected to work on both the Foundation FVP 250 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 251 * SYS_ID register provides a mechanism for detecting the differences between 252 * these platforms. This information is stored in a per-BL array to allow the 253 * code to take the correct path.Per BL platform configuration. 254 ******************************************************************************/ 255 void __init fvp_config_setup(void) 256 { 257 unsigned int rev, hbi, bld, arch, sys_id; 258 259 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 260 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 261 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 262 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 263 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 264 265 if (arch != ARCH_MODEL) { 266 ERROR("This firmware is for FVP models\n"); 267 panic(); 268 } 269 270 /* 271 * The build field in the SYS_ID tells which variant of the GIC 272 * memory is implemented by the model. 273 */ 274 switch (bld) { 275 case BLD_GIC_VE_MMAP: 276 ERROR("Legacy Versatile Express memory map for GIC peripheral" 277 " is not supported\n"); 278 panic(); 279 break; 280 case BLD_GIC_A53A57_MMAP: 281 break; 282 default: 283 ERROR("Unsupported board build %x\n", bld); 284 panic(); 285 } 286 287 /* 288 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 289 * for the Foundation FVP. 290 */ 291 switch (hbi) { 292 case HBI_FOUNDATION_FVP: 293 arm_config.flags = 0; 294 295 /* 296 * Check for supported revisions of Foundation FVP 297 * Allow future revisions to run but emit warning diagnostic 298 */ 299 switch (rev) { 300 case REV_FOUNDATION_FVP_V2_0: 301 case REV_FOUNDATION_FVP_V2_1: 302 case REV_FOUNDATION_FVP_v9_1: 303 case REV_FOUNDATION_FVP_v9_6: 304 break; 305 default: 306 WARN("Unrecognized Foundation FVP revision %x\n", rev); 307 break; 308 } 309 break; 310 case HBI_BASE_FVP: 311 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 312 313 /* 314 * Check for supported revisions 315 * Allow future revisions to run but emit warning diagnostic 316 */ 317 switch (rev) { 318 case REV_BASE_FVP_V0: 319 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 320 break; 321 case REV_BASE_FVP_REVC: 322 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 323 ARM_CONFIG_FVP_HAS_CCI5XX); 324 break; 325 default: 326 WARN("Unrecognized Base FVP revision %x\n", rev); 327 break; 328 } 329 break; 330 default: 331 ERROR("Unsupported board HBI number 0x%x\n", hbi); 332 panic(); 333 } 334 335 /* 336 * We assume that the presence of MT bit, and therefore shifted 337 * affinities, is uniform across the platform: either all CPUs, or no 338 * CPUs implement it. 339 */ 340 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 341 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 342 } 343 344 345 void __init fvp_interconnect_init(void) 346 { 347 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 348 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 349 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 350 panic(); 351 } 352 353 plat_arm_interconnect_init(); 354 #else 355 uintptr_t cci_base = 0U; 356 const int *cci_map = NULL; 357 unsigned int map_size = 0U; 358 359 /* Initialize the right interconnect */ 360 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 361 cci_base = PLAT_FVP_CCI5XX_BASE; 362 cci_map = fvp_cci5xx_map; 363 map_size = ARRAY_SIZE(fvp_cci5xx_map); 364 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 365 cci_base = PLAT_FVP_CCI400_BASE; 366 cci_map = fvp_cci400_map; 367 map_size = ARRAY_SIZE(fvp_cci400_map); 368 } else { 369 return; 370 } 371 372 assert(cci_base != 0U); 373 assert(cci_map != NULL); 374 cci_init(cci_base, cci_map, map_size); 375 #endif 376 } 377 378 void fvp_interconnect_enable(void) 379 { 380 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 381 plat_arm_interconnect_enter_coherency(); 382 #else 383 unsigned int master; 384 385 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 386 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 387 master = get_interconnect_master(); 388 cci_enable_snoop_dvm_reqs(master); 389 } 390 #endif 391 } 392 393 void fvp_interconnect_disable(void) 394 { 395 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 396 plat_arm_interconnect_exit_coherency(); 397 #else 398 unsigned int master; 399 400 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 401 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 402 master = get_interconnect_master(); 403 cci_disable_snoop_dvm_reqs(master); 404 } 405 #endif 406 } 407 408 #if TRUSTED_BOARD_BOOT 409 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 410 { 411 assert(heap_addr != NULL); 412 assert(heap_size != NULL); 413 414 return arm_get_mbedtls_heap(heap_addr, heap_size); 415 } 416 #endif 417 418 void fvp_timer_init(void) 419 { 420 #if FVP_USE_SP804_TIMER 421 /* Enable the clock override for SP804 timer 0, which means that no 422 * clock dividers are applied and the raw (35MHz) clock will be used. 423 */ 424 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 425 426 /* Initialize delay timer driver using SP804 dual timer 0 */ 427 sp804_timer_init(V2M_SP804_TIMER0_BASE, 428 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 429 #else 430 generic_delay_timer_init(); 431 432 /* Enable System level generic timer */ 433 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 434 CNTCR_FCREQ(0U) | CNTCR_EN); 435 #endif /* FVP_USE_SP804_TIMER */ 436 } 437