1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <arm_spm_def.h> 10 #include <assert.h> 11 #include <cci.h> 12 #include <ccn.h> 13 #include <debug.h> 14 #include <gicv2.h> 15 #include <mmio.h> 16 #include <plat_arm.h> 17 #include <platform.h> 18 #include <secure_partition.h> 19 #include <v2m_def.h> 20 #include <xlat_tables_compat.h> 21 22 #include "../fvp_def.h" 23 #include "fvp_private.h" 24 25 /* Defines for GIC Driver build time selection */ 26 #define FVP_GICV2 1 27 #define FVP_GICV3 2 28 29 /******************************************************************************* 30 * arm_config holds the characteristics of the differences between the three FVP 31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 32 * at each boot stage by the primary before enabling the MMU (to allow 33 * interconnect configuration) & used thereafter. Each BL will have its own copy 34 * to allow independent operation. 35 ******************************************************************************/ 36 arm_config_t arm_config; 37 38 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 39 DEVICE0_SIZE, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 43 DEVICE1_SIZE, \ 44 MT_DEVICE | MT_RW | MT_SECURE) 45 46 /* 47 * Need to be mapped with write permissions in order to set a new non-volatile 48 * counter value. 49 */ 50 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 51 DEVICE2_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE) 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 57 * of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef AARCH64 87 ARM_MAP_DRAM2, 88 #endif 89 #ifdef SPD_tspd 90 ARM_MAP_TSP_SEC_MEM, 91 #endif 92 #if TRUSTED_BOARD_BOOT 93 /* To access the Root of Trust Public Key registers. */ 94 MAP_DEVICE2, 95 #if !BL2_AT_EL3 96 ARM_MAP_BL1_RW, 97 #endif 98 #endif /* TRUSTED_BOARD_BOOT */ 99 #if ENABLE_SPM 100 ARM_SP_IMAGE_MMAP, 101 #endif 102 #if ARM_BL31_IN_DRAM 103 ARM_MAP_BL31_SEC_DRAM, 104 #endif 105 #ifdef SPD_opteed 106 ARM_MAP_OPTEE_CORE_MEM, 107 ARM_OPTEE_PAGEABLE_LOAD_MEM, 108 #endif 109 {0} 110 }; 111 #endif 112 #ifdef IMAGE_BL2U 113 const mmap_region_t plat_arm_mmap[] = { 114 MAP_DEVICE0, 115 V2M_MAP_IOFPGA, 116 {0} 117 }; 118 #endif 119 #ifdef IMAGE_BL31 120 const mmap_region_t plat_arm_mmap[] = { 121 ARM_MAP_SHARED_RAM, 122 ARM_MAP_EL3_TZC_DRAM, 123 V2M_MAP_IOFPGA, 124 MAP_DEVICE0, 125 MAP_DEVICE1, 126 ARM_V2M_MAP_MEM_PROTECT, 127 #if ENABLE_SPM && SPM_DEPRECATED 128 ARM_SPM_BUF_EL3_MMAP, 129 #endif 130 {0} 131 }; 132 133 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 134 const mmap_region_t plat_arm_secure_partition_mmap[] = { 135 V2M_MAP_IOFPGA_EL0, /* for the UART */ 136 MAP_REGION_FLAT(DEVICE0_BASE, \ 137 DEVICE0_SIZE, \ 138 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 139 ARM_SP_IMAGE_MMAP, 140 ARM_SP_IMAGE_NS_BUF_MMAP, 141 ARM_SP_IMAGE_RW_MMAP, 142 ARM_SPM_BUF_EL0_MMAP, 143 {0} 144 }; 145 #endif 146 #endif 147 #ifdef IMAGE_BL32 148 const mmap_region_t plat_arm_mmap[] = { 149 #ifdef AARCH32 150 ARM_MAP_SHARED_RAM, 151 ARM_V2M_MAP_MEM_PROTECT, 152 #endif 153 V2M_MAP_IOFPGA, 154 MAP_DEVICE0, 155 MAP_DEVICE1, 156 {0} 157 }; 158 #endif 159 160 ARM_CASSERT_MMAP 161 162 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 163 static const int fvp_cci400_map[] = { 164 PLAT_FVP_CCI400_CLUS0_SL_PORT, 165 PLAT_FVP_CCI400_CLUS1_SL_PORT, 166 }; 167 168 static const int fvp_cci5xx_map[] = { 169 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 170 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 171 }; 172 173 static unsigned int get_interconnect_master(void) 174 { 175 unsigned int master; 176 u_register_t mpidr; 177 178 mpidr = read_mpidr_el1(); 179 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 180 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 181 182 assert(master < FVP_CLUSTER_COUNT); 183 return master; 184 } 185 #endif 186 187 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 188 /* 189 * Boot information passed to a secure partition during initialisation. Linear 190 * indices in MP information will be filled at runtime. 191 */ 192 static secure_partition_mp_info_t sp_mp_info[] = { 193 [0] = {0x80000000, 0}, 194 [1] = {0x80000001, 0}, 195 [2] = {0x80000002, 0}, 196 [3] = {0x80000003, 0}, 197 [4] = {0x80000100, 0}, 198 [5] = {0x80000101, 0}, 199 [6] = {0x80000102, 0}, 200 [7] = {0x80000103, 0}, 201 }; 202 203 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 204 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 205 .h.version = VERSION_1, 206 .h.size = sizeof(secure_partition_boot_info_t), 207 .h.attr = 0, 208 .sp_mem_base = ARM_SP_IMAGE_BASE, 209 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 210 .sp_image_base = ARM_SP_IMAGE_BASE, 211 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 212 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 213 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE, 214 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 215 .sp_image_size = ARM_SP_IMAGE_SIZE, 216 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 217 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 218 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE, 219 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 220 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 221 .num_cpus = PLATFORM_CORE_COUNT, 222 .mp_info = &sp_mp_info[0], 223 }; 224 225 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 226 { 227 return plat_arm_secure_partition_mmap; 228 } 229 230 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 231 void *cookie) 232 { 233 return &plat_arm_secure_partition_boot_info; 234 } 235 #endif 236 237 /******************************************************************************* 238 * A single boot loader stack is expected to work on both the Foundation FVP 239 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 240 * SYS_ID register provides a mechanism for detecting the differences between 241 * these platforms. This information is stored in a per-BL array to allow the 242 * code to take the correct path.Per BL platform configuration. 243 ******************************************************************************/ 244 void __init fvp_config_setup(void) 245 { 246 unsigned int rev, hbi, bld, arch, sys_id; 247 248 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 249 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 250 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 251 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 252 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 253 254 if (arch != ARCH_MODEL) { 255 ERROR("This firmware is for FVP models\n"); 256 panic(); 257 } 258 259 /* 260 * The build field in the SYS_ID tells which variant of the GIC 261 * memory is implemented by the model. 262 */ 263 switch (bld) { 264 case BLD_GIC_VE_MMAP: 265 ERROR("Legacy Versatile Express memory map for GIC peripheral" 266 " is not supported\n"); 267 panic(); 268 break; 269 case BLD_GIC_A53A57_MMAP: 270 break; 271 default: 272 ERROR("Unsupported board build %x\n", bld); 273 panic(); 274 } 275 276 /* 277 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 278 * for the Foundation FVP. 279 */ 280 switch (hbi) { 281 case HBI_FOUNDATION_FVP: 282 arm_config.flags = 0; 283 284 /* 285 * Check for supported revisions of Foundation FVP 286 * Allow future revisions to run but emit warning diagnostic 287 */ 288 switch (rev) { 289 case REV_FOUNDATION_FVP_V2_0: 290 case REV_FOUNDATION_FVP_V2_1: 291 case REV_FOUNDATION_FVP_v9_1: 292 case REV_FOUNDATION_FVP_v9_6: 293 break; 294 default: 295 WARN("Unrecognized Foundation FVP revision %x\n", rev); 296 break; 297 } 298 break; 299 case HBI_BASE_FVP: 300 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 301 302 /* 303 * Check for supported revisions 304 * Allow future revisions to run but emit warning diagnostic 305 */ 306 switch (rev) { 307 case REV_BASE_FVP_V0: 308 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 309 break; 310 case REV_BASE_FVP_REVC: 311 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 312 ARM_CONFIG_FVP_HAS_CCI5XX); 313 break; 314 default: 315 WARN("Unrecognized Base FVP revision %x\n", rev); 316 break; 317 } 318 break; 319 default: 320 ERROR("Unsupported board HBI number 0x%x\n", hbi); 321 panic(); 322 } 323 324 /* 325 * We assume that the presence of MT bit, and therefore shifted 326 * affinities, is uniform across the platform: either all CPUs, or no 327 * CPUs implement it. 328 */ 329 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 330 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 331 } 332 333 334 void __init fvp_interconnect_init(void) 335 { 336 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 337 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 338 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 339 panic(); 340 } 341 342 plat_arm_interconnect_init(); 343 #else 344 uintptr_t cci_base = 0U; 345 const int *cci_map = NULL; 346 unsigned int map_size = 0U; 347 348 /* Initialize the right interconnect */ 349 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 350 cci_base = PLAT_FVP_CCI5XX_BASE; 351 cci_map = fvp_cci5xx_map; 352 map_size = ARRAY_SIZE(fvp_cci5xx_map); 353 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 354 cci_base = PLAT_FVP_CCI400_BASE; 355 cci_map = fvp_cci400_map; 356 map_size = ARRAY_SIZE(fvp_cci400_map); 357 } else { 358 return; 359 } 360 361 assert(cci_base != 0U); 362 assert(cci_map != NULL); 363 cci_init(cci_base, cci_map, map_size); 364 #endif 365 } 366 367 void fvp_interconnect_enable(void) 368 { 369 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 370 plat_arm_interconnect_enter_coherency(); 371 #else 372 unsigned int master; 373 374 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 375 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 376 master = get_interconnect_master(); 377 cci_enable_snoop_dvm_reqs(master); 378 } 379 #endif 380 } 381 382 void fvp_interconnect_disable(void) 383 { 384 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 385 plat_arm_interconnect_exit_coherency(); 386 #else 387 unsigned int master; 388 389 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 390 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 391 master = get_interconnect_master(); 392 cci_disable_snoop_dvm_reqs(master); 393 } 394 #endif 395 } 396 397 #if TRUSTED_BOARD_BOOT 398 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 399 { 400 assert(heap_addr != NULL); 401 assert(heap_size != NULL); 402 403 return arm_get_mbedtls_heap(heap_addr, heap_size); 404 } 405 #endif 406