1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <drivers/arm/smmu_v3.h> 10 #include <fconf_hw_config_getter.h> 11 #include <lib/fconf/fconf.h> 12 #include <lib/fconf/fconf_dyn_cfg_getter.h> 13 #include <lib/mmio.h> 14 #include <plat/arm/common/arm_config.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #include "fvp_private.h" 19 20 void __init bl31_early_platform_setup2(u_register_t arg0, 21 u_register_t arg1, u_register_t arg2, u_register_t arg3) 22 { 23 #if !RESET_TO_BL31 && !BL2_AT_EL3 24 const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 25 26 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 27 /* Fill the properties struct with the info from the config dtb */ 28 fconf_populate("FW_CONFIG", arg1); 29 30 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 31 if (soc_fw_config_info != NULL) { 32 arg1 = soc_fw_config_info->config_addr; 33 } 34 #endif /* !RESET_TO_BL31 && !BL2_AT_EL3 */ 35 36 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 37 38 /* Initialize the platform config for future decision making */ 39 fvp_config_setup(); 40 41 /* 42 * Initialize the correct interconnect for this cluster during cold 43 * boot. No need for locks as no other CPU is active. 44 */ 45 fvp_interconnect_init(); 46 47 /* 48 * Enable coherency in interconnect for the primary CPU's cluster. 49 * Earlier bootloader stages might already do this (e.g. Trusted 50 * Firmware's BL1 does it) but we can't assume so. There is no harm in 51 * executing this code twice anyway. 52 * FVP PSCI code will enable coherency for other clusters. 53 */ 54 fvp_interconnect_enable(); 55 56 /* Initialize System level generic or SP804 timer */ 57 fvp_timer_init(); 58 59 /* On FVP RevC, initialize SMMUv3 */ 60 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) 61 smmuv3_init(PLAT_FVP_SMMUV3_BASE); 62 } 63 64 void __init bl31_plat_arch_setup(void) 65 { 66 arm_bl31_plat_arch_setup(); 67 68 /* 69 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run. 70 * So there is no BL2 to load the HW_CONFIG dtb into memory before 71 * control is passed to BL31. 72 */ 73 #if !RESET_TO_BL31 && !BL2_AT_EL3 74 /* HW_CONFIG was also loaded by BL2 */ 75 const struct dyn_cfg_dtb_info_t *hw_config_info; 76 77 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 78 assert(hw_config_info != NULL); 79 80 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 81 #endif 82 } 83 84 unsigned int plat_get_syscnt_freq2(void) 85 { 86 unsigned int counter_base_frequency; 87 88 #if !RESET_TO_BL31 && !BL2_AT_EL3 89 /* Get the frequency through FCONF API for HW_CONFIG */ 90 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq); 91 if (counter_base_frequency > 0U) { 92 return counter_base_frequency; 93 } 94 #endif 95 96 /* Read the frequency from Frequency modes table */ 97 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 98 99 /* The first entry of the frequency modes table must not be 0 */ 100 if (counter_base_frequency == 0U) { 101 panic(); 102 } 103 104 return counter_base_frequency; 105 } 106