1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/arm/sp804_delay_timer.h> 12 #include <fvp_pas_def.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/transfer_list.h> 16 17 #include <plat/arm/common/plat_arm.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 21 #include "fvp_private.h" 22 23 static struct transfer_list_header *ns_tl __unused; 24 25 #if ENABLE_RME 26 /* 27 * The GPT library might modify the gpt regions structure to optimize 28 * the layout, so the array cannot be constant. 29 */ 30 static pas_region_t pas_regions[] = { 31 ARM_PAS_KERNEL, 32 ARM_PAS_SECURE, 33 ARM_PAS_REALM, 34 ARM_PAS_EL3_DRAM, 35 ARM_PAS_GPTS, 36 ARM_PAS_KERNEL_1 37 }; 38 39 static const arm_gpt_info_t arm_gpt_info = { 40 .pas_region_base = pas_regions, 41 .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions), 42 .l0_base = (uintptr_t)ARM_L0_GPT_BASE, 43 .l1_base = (uintptr_t)ARM_L1_GPT_BASE, 44 .l0_size = (size_t)ARM_L0_GPT_SIZE, 45 .l1_size = (size_t)ARM_L1_GPT_SIZE, 46 .pps = GPCCR_PPS_64GB, 47 .pgs = GPCCR_PGS_4K 48 }; 49 #endif 50 51 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 52 { 53 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 54 55 /* Initialize the platform config for future decision making */ 56 fvp_config_setup(); 57 } 58 59 void bl2_platform_setup(void) 60 { 61 arm_bl2_platform_setup(); 62 63 #if TRANSFER_LIST 64 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE); 65 assert(ns_tl != NULL); 66 #endif 67 /* Initialize System level generic or SP804 timer */ 68 fvp_timer_init(); 69 } 70 71 #if ENABLE_RME 72 const arm_gpt_info_t *plat_arm_get_gpt_info(void) 73 { 74 return &arm_gpt_info; 75 } 76 #endif /* ENABLE_RME */ 77 78 /******************************************************************************* 79 * This function returns the list of executable images 80 ******************************************************************************/ 81 struct bl_params *plat_get_next_bl_params(void) 82 { 83 struct bl_params *arm_bl_params; 84 const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 85 struct transfer_list_entry *te __unused; 86 bl_mem_params_node_t *param_node __unused; 87 88 arm_bl_params = arm_get_next_bl_params(); 89 90 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE 91 const struct dyn_cfg_dtb_info_t *fw_config_info; 92 uintptr_t fw_config_base = 0UL; 93 94 #if __aarch64__ 95 /* Get BL31 image node */ 96 param_node = get_bl_mem_params_node(BL31_IMAGE_ID); 97 #else /* aarch32 */ 98 /* Get SP_MIN image node */ 99 param_node = get_bl_mem_params_node(BL32_IMAGE_ID); 100 #endif /* __aarch64__ */ 101 assert(param_node != NULL); 102 103 /* Update the next image's ep info with the FW config address */ 104 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); 105 assert(fw_config_info != NULL); 106 107 fw_config_base = fw_config_info->config_addr; 108 assert(fw_config_base != 0UL); 109 110 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; 111 112 /* Update BL33's ep info with the NS HW config address */ 113 param_node = get_bl_mem_params_node(BL33_IMAGE_ID); 114 assert(param_node != NULL); 115 116 #if TRANSFER_LIST 117 /* Update BL33's ep info with NS HW config address */ 118 te = transfer_list_find(ns_tl, TL_TAG_FDT); 119 assert(te != NULL); 120 121 param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE | 122 REGISTER_CONVENTION_VERSION_MASK; 123 param_node->ep_info.args.arg2 = 0; 124 param_node->ep_info.args.arg3 = (uintptr_t)ns_tl; 125 param_node->ep_info.args.arg0 = 126 te ? (uintptr_t)transfer_list_entry_data(te) : 0; 127 #else 128 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 129 assert(hw_config_info != NULL); 130 131 param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr; 132 #endif /* TRANSFER_LIST */ 133 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */ 134 135 return arm_bl_params; 136 } 137 138 int bl2_plat_handle_post_image_load(unsigned int image_id) 139 { 140 #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE 141 if (image_id == HW_CONFIG_ID) { 142 const struct dyn_cfg_dtb_info_t *hw_config_info; 143 struct transfer_list_entry *te __unused; 144 145 const bl_mem_params_node_t *param_node = 146 get_bl_mem_params_node(image_id); 147 assert(param_node != NULL); 148 149 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 150 assert(hw_config_info != NULL); 151 152 #if TRANSFER_LIST 153 /* Update BL33's ep info with NS HW config address */ 154 te = transfer_list_add(ns_tl, TL_TAG_FDT, 155 param_node->image_info.image_size, 156 (void *)hw_config_info->config_addr); 157 assert(te != NULL); 158 #else 159 memcpy((void *)hw_config_info->secondary_config_addr, 160 (void *)hw_config_info->config_addr, 161 (size_t)param_node->image_info.image_size); 162 163 /* 164 * Ensure HW-config device tree is committed to memory, as the HW-Config 165 * might be used without cache and MMU enabled at BL33. 166 */ 167 flush_dcache_range(hw_config_info->secondary_config_addr, 168 param_node->image_info.image_size); 169 #endif /* TRANSFER_LIST */ 170 } 171 #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */ 172 173 return arm_bl2_plat_handle_post_image_load(image_id); 174 } 175