13fc4124cSDan Handley /* 2*0c306cc0SSoby Mathew * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 33fc4124cSDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53fc4124cSDan Handley */ 63fc4124cSDan Handley 732cd95f0SAntonio Nino Diaz #include <generic_delay_timer.h> 8540a5ba8SJuan Castillo #include <mmio.h> 93fc4124cSDan Handley #include <plat_arm.h> 10b49b3221SRyan Harkin #include <sp804_delay_timer.h> 11b49b3221SRyan Harkin #include <v2m_def.h> 12b49b3221SRyan Harkin #include "fvp_def.h" 133fc4124cSDan Handley #include "fvp_private.h" 143fc4124cSDan Handley 15*0c306cc0SSoby Mathew void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 163fc4124cSDan Handley { 17*0c306cc0SSoby Mathew arm_bl2_early_platform_setup((meminfo_t *)arg1); 183fc4124cSDan Handley 193fc4124cSDan Handley /* Initialize the platform config for future decision making */ 203fc4124cSDan Handley fvp_config_setup(); 213fc4124cSDan Handley } 22b49b3221SRyan Harkin 23b49b3221SRyan Harkin void bl2_platform_setup(void) 24b49b3221SRyan Harkin { 25b49b3221SRyan Harkin arm_bl2_platform_setup(); 26b49b3221SRyan Harkin 2732cd95f0SAntonio Nino Diaz #if FVP_USE_SP804_TIMER 28540a5ba8SJuan Castillo /* Enable the clock override for SP804 timer 0, which means that no 29540a5ba8SJuan Castillo * clock dividers are applied and the raw (35 MHz) clock will be used */ 30540a5ba8SJuan Castillo mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 31540a5ba8SJuan Castillo 32b49b3221SRyan Harkin /* Initialize delay timer driver using SP804 dual timer 0 */ 33b49b3221SRyan Harkin sp804_timer_init(V2M_SP804_TIMER0_BASE, 34b49b3221SRyan Harkin SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 3532cd95f0SAntonio Nino Diaz #else 3632cd95f0SAntonio Nino Diaz generic_delay_timer_init(); 3732cd95f0SAntonio Nino Diaz #endif /* FVP_USE_SP804_TIMER */ 38b49b3221SRyan Harkin } 39