xref: /rk3399_ARM-atf/plat/arm/board/fvp/fvp_bl1_setup.c (revision bd9344f670a46125cdd8949ded75be124f34d587)
13fc4124cSDan Handley /*
21af540efSRoberto Vargas  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
33fc4124cSDan Handley  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
53fc4124cSDan Handley  */
63fc4124cSDan Handley 
709d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h>
8*bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h>
909d40e0eSAntonio Nino Diaz #include <plat/common/platform.h>
103fc4124cSDan Handley 
1109d40e0eSAntonio Nino Diaz #include "fvp_private.h"
123fc4124cSDan Handley 
133fc4124cSDan Handley /*******************************************************************************
143fc4124cSDan Handley  * Perform any BL1 specific platform actions.
153fc4124cSDan Handley  ******************************************************************************/
163fc4124cSDan Handley void bl1_early_platform_setup(void)
173fc4124cSDan Handley {
183fc4124cSDan Handley 	arm_bl1_early_platform_setup();
193fc4124cSDan Handley 
203fc4124cSDan Handley 	/* Initialize the platform config for future decision making */
213fc4124cSDan Handley 	fvp_config_setup();
223fc4124cSDan Handley 
233fc4124cSDan Handley 	/*
246355f234SVikram Kanigiri 	 * Initialize Interconnect for this cluster during cold boot.
253fc4124cSDan Handley 	 * No need for locks as no other CPU is active.
263fc4124cSDan Handley 	 */
276355f234SVikram Kanigiri 	fvp_interconnect_init();
283fc4124cSDan Handley 	/*
296355f234SVikram Kanigiri 	 * Enable coherency in Interconnect for the primary CPU's cluster.
303fc4124cSDan Handley 	 */
316355f234SVikram Kanigiri 	fvp_interconnect_enable();
323fc4124cSDan Handley }
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