xref: /rk3399_ARM-atf/plat/arm/board/fvp/fvp_bl1_setup.c (revision b0c97dafe00f5da71361b53fcbf5e4c12b174ec2)
13fc4124cSDan Handley /*
21af540efSRoberto Vargas  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
33fc4124cSDan Handley  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
53fc4124cSDan Handley  */
63fc4124cSDan Handley 
709d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h>
8*b0c97dafSAditya Angadi #include <drivers/arm/sp805.h>
9bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h>
10*b0c97dafSAditya Angadi #include <plat/arm/common/arm_def.h>
1109d40e0eSAntonio Nino Diaz #include <plat/common/platform.h>
1209d40e0eSAntonio Nino Diaz #include "fvp_private.h"
133fc4124cSDan Handley 
143fc4124cSDan Handley /*******************************************************************************
153fc4124cSDan Handley  * Perform any BL1 specific platform actions.
163fc4124cSDan Handley  ******************************************************************************/
173fc4124cSDan Handley void bl1_early_platform_setup(void)
183fc4124cSDan Handley {
193fc4124cSDan Handley 	arm_bl1_early_platform_setup();
203fc4124cSDan Handley 
213fc4124cSDan Handley 	/* Initialize the platform config for future decision making */
223fc4124cSDan Handley 	fvp_config_setup();
233fc4124cSDan Handley 
243fc4124cSDan Handley 	/*
256355f234SVikram Kanigiri 	 * Initialize Interconnect for this cluster during cold boot.
263fc4124cSDan Handley 	 * No need for locks as no other CPU is active.
273fc4124cSDan Handley 	 */
286355f234SVikram Kanigiri 	fvp_interconnect_init();
293fc4124cSDan Handley 	/*
306355f234SVikram Kanigiri 	 * Enable coherency in Interconnect for the primary CPU's cluster.
313fc4124cSDan Handley 	 */
326355f234SVikram Kanigiri 	fvp_interconnect_enable();
333fc4124cSDan Handley }
34*b0c97dafSAditya Angadi 
35*b0c97dafSAditya Angadi void plat_arm_secure_wdt_start(void)
36*b0c97dafSAditya Angadi {
37*b0c97dafSAditya Angadi 	sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
38*b0c97dafSAditya Angadi }
39*b0c97dafSAditya Angadi 
40*b0c97dafSAditya Angadi void plat_arm_secure_wdt_stop(void)
41*b0c97dafSAditya Angadi {
42*b0c97dafSAditya Angadi 	sp805_stop(ARM_SP805_TWDG_BASE);
43*b0c97dafSAditya Angadi }
44