13fc4124cSDan Handley /* 2*1461ad9fSAlexei Fedorov * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 33fc4124cSDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53fc4124cSDan Handley */ 63fc4124cSDan Handley 709d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 8*1461ad9fSAlexei Fedorov #include <drivers/arm/smmu_v3.h> 9b0c97dafSAditya Angadi #include <drivers/arm/sp805.h> 10*1461ad9fSAlexei Fedorov #include <plat/arm/common/arm_config.h> 11bd9344f6SAntonio Nino Diaz #include <plat/arm/common/plat_arm.h> 12b0c97dafSAditya Angadi #include <plat/arm/common/arm_def.h> 1309d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 1409d40e0eSAntonio Nino Diaz #include "fvp_private.h" 153fc4124cSDan Handley 163fc4124cSDan Handley /******************************************************************************* 173fc4124cSDan Handley * Perform any BL1 specific platform actions. 183fc4124cSDan Handley ******************************************************************************/ 193fc4124cSDan Handley void bl1_early_platform_setup(void) 203fc4124cSDan Handley { 213fc4124cSDan Handley arm_bl1_early_platform_setup(); 223fc4124cSDan Handley 233fc4124cSDan Handley /* Initialize the platform config for future decision making */ 243fc4124cSDan Handley fvp_config_setup(); 253fc4124cSDan Handley 263fc4124cSDan Handley /* 276355f234SVikram Kanigiri * Initialize Interconnect for this cluster during cold boot. 283fc4124cSDan Handley * No need for locks as no other CPU is active. 293fc4124cSDan Handley */ 306355f234SVikram Kanigiri fvp_interconnect_init(); 313fc4124cSDan Handley /* 326355f234SVikram Kanigiri * Enable coherency in Interconnect for the primary CPU's cluster. 333fc4124cSDan Handley */ 346355f234SVikram Kanigiri fvp_interconnect_enable(); 353fc4124cSDan Handley } 36b0c97dafSAditya Angadi 37b0c97dafSAditya Angadi void plat_arm_secure_wdt_start(void) 38b0c97dafSAditya Angadi { 39b0c97dafSAditya Angadi sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 40b0c97dafSAditya Angadi } 41b0c97dafSAditya Angadi 42b0c97dafSAditya Angadi void plat_arm_secure_wdt_stop(void) 43b0c97dafSAditya Angadi { 44b0c97dafSAditya Angadi sp805_stop(ARM_SP805_TWDG_BASE); 45b0c97dafSAditya Angadi } 46*1461ad9fSAlexei Fedorov 47*1461ad9fSAlexei Fedorov void bl1_platform_setup(void) 48*1461ad9fSAlexei Fedorov { 49*1461ad9fSAlexei Fedorov arm_bl1_platform_setup(); 50*1461ad9fSAlexei Fedorov 51*1461ad9fSAlexei Fedorov /* On FVP RevC, initialize SMMUv3 */ 52*1461ad9fSAlexei Fedorov if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) 53*1461ad9fSAlexei Fedorov smmuv3_security_init(PLAT_FVP_SMMUV3_BASE); 54*1461ad9fSAlexei Fedorov } 55