1/* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6/dts-v1/; 7 8#define AFF 00 9 10#include "fvp-defs.dtsi" 11#undef POST 12#define POST \ 13 }; 14 15/ { 16 compatible = "arm,ffa-core-manifest-1.0"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 attribute { 21 spmc_id = <0x8000>; 22 maj_ver = <0x1>; 23 min_ver = <0x1>; 24 exec_state = <0x0>; 25 load_address = <0x0 0x6000000>; 26 entrypoint = <0x0 0x6000000>; 27 binary_size = <0x80000>; 28 }; 29 30 hypervisor { 31 compatible = "hafnium,hafnium"; 32 vm1 { 33 is_ffa_partition; 34 debug_name = "cactus-primary"; 35 load_address = <0x7000000>; 36 vcpu_count = <8>; 37 mem_size = <1048576>; 38 }; 39 vm2 { 40 is_ffa_partition; 41 debug_name = "cactus-secondary"; 42 load_address = <0x7100000>; 43 vcpu_count = <8>; 44 mem_size = <1048576>; 45 }; 46 vm3 { 47 is_ffa_partition; 48 debug_name = "cactus-tertiary"; 49 load_address = <0x7200000>; 50 vcpu_count = <1>; 51 mem_size = <1048576>; 52 }; 53 vm4 { 54 is_ffa_partition; 55 debug_name = "ivy"; 56 load_address = <0x7600000>; 57 vcpu_count = <1>; 58 mem_size = <1048576>; 59 }; 60 }; 61 62 cpus { 63 #address-cells = <0x2>; 64 #size-cells = <0x0>; 65 66 CPU_0 67 68 /* 69 * SPMC (Hafnium) requires secondary core nodes are declared 70 * in descending order. 71 */ 72 CPU_7 73 CPU_6 74 CPU_5 75 CPU_4 76 CPU_3 77 CPU_2 78 CPU_1 79 }; 80 81 memory@0 { 82 device_type = "memory"; 83 reg = <0x0 0xfd000000 0x0 0x2000000>, 84 <0x0 0x7000000 0x0 0x1000000>, 85 <0x0 0xff000000 0x0 0x1000000>; 86 }; 87 88 memory@1 { 89 device_type = "ns-memory"; 90 reg = <0x00008800 0x80000000 0x0 0x7f000000>, 91 <0x0 0x88000000 0x0 0x10000000>; 92 }; 93 94#if MEASURED_BOOT 95#include "event_log.dtsi" 96#endif 97}; 98