1/* 2 * Copyright (c) 2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6/dts-v1/; 7 8#define AFF 00 9 10#include "fvp-defs.dtsi" 11#undef POST 12#define POST \ 13 }; 14 15/ { 16 compatible = "arm,ffa-core-manifest-1.0"; 17 #address-cells = <2>; 18 #size-cells = <1>; 19 20 attribute { 21 spmc_id = <0x8000>; 22 maj_ver = <0x1>; 23 min_ver = <0x0>; 24 exec_state = <0x0>; 25 load_address = <0x0 0x6000000>; 26 entrypoint = <0x0 0x6000000>; 27 binary_size = <0x80000>; 28 }; 29 30 chosen { 31 linux,initrd-start = <0>; 32 linux,initrd-end = <0>; 33 }; 34 35 hypervisor { 36 compatible = "hafnium,hafnium"; 37 vm1 { 38 is_ffa_partition; 39 debug_name = "cactus-primary"; 40 load_address = <0x7000000>; 41 }; 42 vm2 { 43 is_ffa_partition; 44 debug_name = "cactus-secondary"; 45 load_address = <0x7100000>; 46 vcpu_count = <8>; 47 mem_size = <1048576>; 48 }; 49 vm3 { 50 is_ffa_partition; 51 debug_name = "cactus-tertiary"; 52 load_address = <0x7200000>; 53 vcpu_count = <8>; 54 mem_size = <1048576>; 55 }; 56 }; 57 58 cpus { 59 #address-cells = <0x2>; 60 #size-cells = <0x0>; 61 62 CPU_0 63 64 /* 65 * SPMC (Hafnium) requires secondary core nodes are declared 66 * in descending order. 67 */ 68 CPU_7 69 CPU_6 70 CPU_5 71 CPU_4 72 CPU_3 73 CPU_2 74 CPU_1 75 }; 76 77 device-memory@0 { 78 device_type = "device-memory"; 79 reg = <0x0 0x0 0x6000000 0x0 0x8000000 0x78000000>; 80 }; 81 82 memory@6000000 { 83 device_type = "memory"; 84 reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ 85 }; 86}; 87