1/* 2 * Copyright (c) 2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6/dts-v1/; 7 8#define AFF 00 9 10#include "fvp-defs.dtsi" 11#undef POST 12#define POST \ 13 }; 14 15/ { 16 compatible = "arm,ffa-core-manifest-1.0"; 17 #address-cells = <2>; 18 #size-cells = <1>; 19 20 attribute { 21 spmc_id = <0x8000>; 22 maj_ver = <0x1>; 23 min_ver = <0x0>; 24 exec_state = <0x0>; 25 load_address = <0x0 0x6000000>; 26 entrypoint = <0x0 0x6000000>; 27 binary_size = <0x80000>; 28 }; 29 30 hypervisor { 31 compatible = "hafnium,hafnium"; 32 vm1 { 33 is_ffa_partition; 34 debug_name = "cactus-primary"; 35 load_address = <0x7000000>; 36 vcpu_count = <8>; 37 mem_size = <1048576>; 38 }; 39 vm2 { 40 is_ffa_partition; 41 debug_name = "cactus-secondary"; 42 load_address = <0x7100000>; 43 vcpu_count = <8>; 44 mem_size = <1048576>; 45 }; 46 vm3 { 47 is_ffa_partition; 48 debug_name = "cactus-tertiary"; 49 load_address = <0x7200000>; 50 vcpu_count = <1>; 51 mem_size = <1048576>; 52 }; 53 }; 54 55 cpus { 56 #address-cells = <0x2>; 57 #size-cells = <0x0>; 58 59 CPU_0 60 61 /* 62 * SPMC (Hafnium) requires secondary core nodes are declared 63 * in descending order. 64 */ 65 CPU_7 66 CPU_6 67 CPU_5 68 CPU_4 69 CPU_3 70 CPU_2 71 CPU_1 72 }; 73 74 memory@6000000 { 75 device_type = "memory"; 76 reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ 77 }; 78}; 79