1/* 2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/tbbr/tbbr_img_def.h> 8#include <platform_def.h> 9 10/dts-v1/; 11 12/ { 13 dtb-registry { 14 compatible = "fconf,dyn_cfg-dtb_registry"; 15 16 tb_fw-config { 17 load-address = <0x0 0x4001300>; 18 max-size = <0x1800>; 19 id = <TB_FW_CONFIG_ID>; 20 }; 21 22 hw-config { 23 load-address = <0x0 0x07f00000>; 24 max-size = <PLAT_ARM_HW_CONFIG_SIZE>; 25 id = <HW_CONFIG_ID>; 26 secondary-load-address = <0x0 0x82000000>; 27 }; 28 29 /* 30 * Load SoC and TOS firmware configs at the base of 31 * non shared SRAM. The runtime checks ensure we don't 32 * overlap BL2, BL31 or BL32. The NT firmware config 33 * is loaded at base of DRAM. 34 */ 35 soc_fw-config { 36 load-address = <0x0 0x04001300>; 37 max-size = <0x200>; 38 id = <SOC_FW_CONFIG_ID>; 39 }; 40 41/* If required, SPD should enable loading of trusted OS fw config */ 42#if defined(SPD_tspd) || defined(SPD_spmd) 43 tos_fw-config { 44 45 load-address = <0x0 0x04001500>; 46#if ENABLE_RME 47 secondary-load-address = <0x0 0x7e00000>; 48#endif /* ENABLE_RME */ 49 max-size = <0xB00>; 50 id = <TOS_FW_CONFIG_ID>; 51 }; 52#endif 53 54 nt_fw-config { 55 load-address = <0x0 0x80000000>; 56 max-size = <0x200>; 57 id = <NT_FW_CONFIG_ID>; 58 }; 59 }; 60}; 61