1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/tbbr/tbbr_img_def.h> 8#include <platform_def.h> 9 10/* DTB load addresses */ 11#define TB_SOC_FW_ADDR (ARM_BL_RAM_BASE + 0x300) 12#define TOS_FW_ADDR (ARM_BL_RAM_BASE + 0x500) 13 14/dts-v1/; 15 16/ { 17 dtb-registry { 18 compatible = "fconf,dyn_cfg-dtb_registry"; 19 20 tb_fw-config { 21 load-address = <0x0 TB_SOC_FW_ADDR>; 22 max-size = <0x1800>; 23 id = <TB_FW_CONFIG_ID>; 24 }; 25 26 hw-config { 27 load-address = <0x0 0x07f00000>; 28 max-size = <PLAT_ARM_HW_CONFIG_SIZE>; 29 id = <HW_CONFIG_ID>; 30 secondary-load-address = <0x0 0x82000000>; 31 }; 32 33 /* 34 * Load SoC and TOS firmware configs at the base of 35 * non shared SRAM. The runtime checks ensure we don't 36 * overlap BL2, BL31 or BL32. The NT firmware config 37 * is loaded at base of DRAM. 38 */ 39 soc_fw-config { 40 load-address = <0x0 TB_SOC_FW_ADDR>; 41 max-size = <0x200>; 42 id = <SOC_FW_CONFIG_ID>; 43 }; 44 45/* If required, SPD should enable loading of trusted OS fw config */ 46#if defined(SPD_tspd) || defined(SPD_spmd) 47 tos_fw-config { 48 load-address = <0x0 TOS_FW_ADDR>; 49#if ENABLE_RME 50 secondary-load-address = <0x0 0x7e00000>; 51#endif /* ENABLE_RME */ 52 max-size = <0xB00>; 53 id = <TOS_FW_CONFIG_ID>; 54 }; 55#endif 56 nt_fw-config { 57 load-address = <0x0 0x80000000>; 58 max-size = <0x200>; 59 id = <NT_FW_CONFIG_ID>; 60 }; 61 }; 62}; 63