1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <gicv2.h> 34#include <gicv3.h> 35#include <platform_def.h> 36#include <v2m_def.h> 37#include "../drivers/pwrc/fvp_pwrc.h" 38#include "../fvp_def.h" 39 40 .globl plat_secondary_cold_boot_setup 41 .globl plat_get_my_entrypoint 42 .globl plat_is_my_cpu_primary 43 44 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res 45 ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID 46 ldr \w_tmp, [\x_tmp] 47 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH 48 cmp \w_tmp, #BLD_GIC_VE_MMAP 49 csel \res, \param1, \param2, eq 50 .endm 51 52 /* ----------------------------------------------------- 53 * void plat_secondary_cold_boot_setup (void); 54 * 55 * This function performs any platform specific actions 56 * needed for a secondary cpu after a cold reset e.g 57 * mark the cpu's presence, mechanism to place it in a 58 * holding pen etc. 59 * TODO: Should we read the PSYS register to make sure 60 * that the request has gone through. 61 * ----------------------------------------------------- 62 */ 63func plat_secondary_cold_boot_setup 64#ifndef EL3_PAYLOAD_BASE 65 /* --------------------------------------------- 66 * Power down this cpu. 67 * TODO: Do we need to worry about powering the 68 * cluster down as well here. That will need 69 * locks which we won't have unless an elf- 70 * loader zeroes out the zi section. 71 * --------------------------------------------- 72 */ 73 mrs x0, mpidr_el1 74 ldr x1, =PWRC_BASE 75 str w0, [x1, #PPOFFR_OFF] 76 77 /* --------------------------------------------- 78 * Disable GIC bypass as well 79 * --------------------------------------------- 80 */ 81 /* Check for GICv3 system register access */ 82 mrs x0, id_aa64pfr0_el1 83 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 84 cmp x0, #1 85 b.ne gicv2_bypass_disable 86 87 /* Check for SRE enable */ 88 mrs x1, ICC_SRE_EL3 89 tst x1, #ICC_SRE_SRE_BIT 90 b.eq gicv2_bypass_disable 91 92 mrs x2, ICC_SRE_EL3 93 orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT) 94 msr ICC_SRE_EL3, x2 95 b secondary_cold_boot_wait 96 97gicv2_bypass_disable: 98 ldr x0, =VE_GICC_BASE 99 ldr x1, =BASE_GICC_BASE 100 fvp_choose_gicmmap x0, x1, x2, w2, x1 101 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) 102 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) 103 str w0, [x1, #GICC_CTLR] 104 105secondary_cold_boot_wait: 106 /* --------------------------------------------- 107 * There is no sane reason to come out of this 108 * wfi so panic if we do. This cpu will be pow- 109 * ered on and reset by the cpu_on pm api 110 * --------------------------------------------- 111 */ 112 dsb sy 113 wfi 114 no_ret plat_panic_handler 115#else 116 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 117 118 /* Wait until the entrypoint gets populated */ 119poll_mailbox: 120 ldr x1, [x0] 121 cbz x1, 1f 122 br x1 1231: 124 wfe 125 b poll_mailbox 126#endif /* EL3_PAYLOAD_BASE */ 127endfunc plat_secondary_cold_boot_setup 128 129 /* --------------------------------------------------------------------- 130 * uintptr_t plat_get_my_entrypoint (void); 131 * 132 * Main job of this routine is to distinguish between a cold and warm 133 * boot. On FVP, this information can be queried from the power 134 * controller. The Power Control SYS Status Register (PSYSR) indicates 135 * the wake-up reason for the CPU. 136 * 137 * For a cold boot, return 0. 138 * For a warm boot, read the mailbox and return the address it contains. 139 * 140 * TODO: PSYSR is a common register and should be 141 * accessed using locks. Since it is not possible 142 * to use locks immediately after a cold reset 143 * we are relying on the fact that after a cold 144 * reset all cpus will read the same WK field 145 * --------------------------------------------------------------------- 146 */ 147func plat_get_my_entrypoint 148 /* --------------------------------------------------------------------- 149 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC 150 * WakeRequest signal" then it is a warm boot. 151 * --------------------------------------------------------------------- 152 */ 153 mrs x2, mpidr_el1 154 ldr x1, =PWRC_BASE 155 str w2, [x1, #PSYSR_OFF] 156 ldr w2, [x1, #PSYSR_OFF] 157 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH 158 cmp w2, #WKUP_PPONR 159 beq warm_reset 160 cmp w2, #WKUP_GICREQ 161 beq warm_reset 162 163 /* Cold reset */ 164 mov x0, #0 165 ret 166 167warm_reset: 168 /* --------------------------------------------------------------------- 169 * A mailbox is maintained in the trusted SRAM. It is flushed out of the 170 * caches after every update using normal memory so it is safe to read 171 * it here with SO attributes. 172 * --------------------------------------------------------------------- 173 */ 174 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 175 ldr x0, [x0] 176 cbz x0, _panic_handler 177 ret 178 179 /* --------------------------------------------------------------------- 180 * The power controller indicates this is a warm reset but the mailbox 181 * is empty. This should never happen! 182 * --------------------------------------------------------------------- 183 */ 184_panic_handler: 185 no_ret plat_panic_handler 186endfunc plat_get_my_entrypoint 187 188 /* ----------------------------------------------------- 189 * unsigned int plat_is_my_cpu_primary (void); 190 * 191 * Find out whether the current cpu is the primary 192 * cpu. 193 * ----------------------------------------------------- 194 */ 195func plat_is_my_cpu_primary 196 mrs x0, mpidr_el1 197 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 198 cmp x0, #FVP_PRIMARY_CPU 199 cset w0, eq 200 ret 201endfunc plat_is_my_cpu_primary 202