1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <platform_def.h> 34#include "../drivers/pwrc/fvp_pwrc.h" 35#include "../fvp_def.h" 36 37 .globl plat_secondary_cold_boot_setup 38 .globl plat_get_my_entrypoint 39 .globl plat_is_my_cpu_primary 40 41 /* -------------------------------------------------------------------- 42 * void plat_secondary_cold_boot_setup (void); 43 * 44 * For AArch32, cold-booting secondary CPUs is not yet 45 * implemented and they panic. 46 * -------------------------------------------------------------------- 47 */ 48func plat_secondary_cold_boot_setup 49cb_panic: 50 b cb_panic 51endfunc plat_secondary_cold_boot_setup 52 53 /* --------------------------------------------------------------------- 54 * unsigned long plat_get_my_entrypoint (void); 55 * 56 * Main job of this routine is to distinguish between a cold and warm 57 * boot. On FVP, this information can be queried from the power 58 * controller. The Power Control SYS Status Register (PSYSR) indicates 59 * the wake-up reason for the CPU. 60 * 61 * For a cold boot, return 0. 62 * For a warm boot, read the mailbox and return the address it contains. 63 * 64 * TODO: PSYSR is a common register and should be 65 * accessed using locks. Since it is not possible 66 * to use locks immediately after a cold reset 67 * we are relying on the fact that after a cold 68 * reset all cpus will read the same WK field 69 * --------------------------------------------------------------------- 70 */ 71func plat_get_my_entrypoint 72 /* --------------------------------------------------------------------- 73 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC 74 * WakeRequest signal" then it is a warm boot. 75 * --------------------------------------------------------------------- 76 */ 77 ldcopr r2, MPIDR 78 ldr r1, =PWRC_BASE 79 str r2, [r1, #PSYSR_OFF] 80 ldr r2, [r1, #PSYSR_OFF] 81 ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH 82 cmp r2, #WKUP_PPONR 83 beq warm_reset 84 cmp r2, #WKUP_GICREQ 85 beq warm_reset 86 87 /* Cold reset */ 88 mov r0, #0 89 bx lr 90 91warm_reset: 92 /* --------------------------------------------------------------------- 93 * A mailbox is maintained in the trusted SRAM. It is flushed out of the 94 * caches after every update using normal memory so it is safe to read 95 * it here with SO attributes. 96 * --------------------------------------------------------------------- 97 */ 98 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE 99 ldr r0, [r0] 100 cmp r0, #0 101 beq _panic 102 bx lr 103 104 /* --------------------------------------------------------------------- 105 * The power controller indicates this is a warm reset but the mailbox 106 * is empty. This should never happen! 107 * --------------------------------------------------------------------- 108 */ 109_panic: 110 b _panic 111endfunc plat_get_my_entrypoint 112 113 /* ----------------------------------------------------- 114 * unsigned int plat_is_my_cpu_primary (void); 115 * 116 * Find out whether the current cpu is the primary 117 * cpu. 118 * ----------------------------------------------------- 119 */ 120func plat_is_my_cpu_primary 121 ldcopr r0, MPIDR 122 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 123 and r0, r1 124 cmp r0, #FVP_PRIMARY_CPU 125 moveq r0, #1 126 movne r0, #0 127 bx lr 128endfunc plat_is_my_cpu_primary 129