1 /*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <plat/arm/common/plat_arm.h>
8 #include <plat/arm/css/common/css_pm.h>
9
10 /******************************************************************************
11 * The power domain tree descriptor.
12 *
13 * This descriptor defines the layout of the power domain tree for the RD1AE
14 * platform, which consists of 16 clusters.
15 ******************************************************************************/
16 const unsigned char rd1_ae_pd_tree_desc[] = {
17 (PLAT_ARM_CLUSTER_COUNT),
18 PLAT_MAX_CPUS_PER_CLUSTER,
19 PLAT_MAX_CPUS_PER_CLUSTER,
20 PLAT_MAX_CPUS_PER_CLUSTER,
21 PLAT_MAX_CPUS_PER_CLUSTER,
22 PLAT_MAX_CPUS_PER_CLUSTER,
23 PLAT_MAX_CPUS_PER_CLUSTER,
24 PLAT_MAX_CPUS_PER_CLUSTER,
25 PLAT_MAX_CPUS_PER_CLUSTER,
26 PLAT_MAX_CPUS_PER_CLUSTER,
27 PLAT_MAX_CPUS_PER_CLUSTER,
28 PLAT_MAX_CPUS_PER_CLUSTER,
29 PLAT_MAX_CPUS_PER_CLUSTER,
30 PLAT_MAX_CPUS_PER_CLUSTER,
31 PLAT_MAX_CPUS_PER_CLUSTER,
32 PLAT_MAX_CPUS_PER_CLUSTER,
33 PLAT_MAX_CPUS_PER_CLUSTER,
34 };
35
36 /*******************************************************************************
37 * This function returns the topology tree information.
38 ******************************************************************************/
plat_get_power_domain_tree_desc(void)39 const unsigned char *plat_get_power_domain_tree_desc(void)
40 {
41 return rd1_ae_pd_tree_desc;
42 }
43
44 /*******************************************************************************
45 * The array mapping platform core position (implemented by plat_my_core_pos())
46 * to the SCMI power domain ID implemented by SCP.
47 ******************************************************************************/
48 const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
49 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
50 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
51 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
52 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
53 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
54 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
55 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
56 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
57 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
58 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
59 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
60 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
61 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
62 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
63 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
64 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
65 };
66
plat_arm_get_cluster_core_count(u_register_t mpidr)67 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
68 {
69 return PLAT_MAX_CPUS_PER_CLUSTER;
70 }
71