1*f45c6d86SAndre Przywara/* 2*f45c6d86SAndre Przywara * Copyright (c) 2020, ARM Limited. All rights reserved. 3*f45c6d86SAndre Przywara * 4*f45c6d86SAndre Przywara * SPDX-License-Identifier: BSD-3-Clause 5*f45c6d86SAndre Przywara * 6*f45c6d86SAndre Przywara * The Arm Ltd. FPGA images start execution at address 0x0, which is 7*f45c6d86SAndre Przywara * mapped at an (emulated) ROM image. The payload uploader can write to 8*f45c6d86SAndre Przywara * this memory, but write access by the CPU cores is prohibited. 9*f45c6d86SAndre Przywara * 10*f45c6d86SAndre Przywara * Provide a simple trampoline to start BL31 execution at the actual 11*f45c6d86SAndre Przywara * load address. We put the DTB address in x0, so any code in DRAM could 12*f45c6d86SAndre Przywara * make use of that information (not yet used in BL31 right now). 13*f45c6d86SAndre Przywara */ 14*f45c6d86SAndre Przywara 15*f45c6d86SAndre Przywara#include <asm_macros.S> 16*f45c6d86SAndre Przywara#include <common/bl_common.ld.h> 17*f45c6d86SAndre Przywara 18*f45c6d86SAndre Przywara.text 19*f45c6d86SAndre Przywara.global _start 20*f45c6d86SAndre Przywara 21*f45c6d86SAndre Przywara_start: 22*f45c6d86SAndre Przywara mov_imm x1, BL31_BASE /* beginning of DRAM */ 23*f45c6d86SAndre Przywara mov_imm x0, FPGA_PRELOADED_DTB_BASE 24*f45c6d86SAndre Przywara br x1 25