1# 2# Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8include lib/libfdt/libfdt.mk 9 10RESET_TO_BL31 := 1 11ifeq (${RESET_TO_BL31}, 0) 12$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") 13endif 14 15ifeq (${ENABLE_PIE}, 1) 16override SEPARATE_CODE_AND_RODATA := 1 17endif 18 19CTX_INCLUDE_AARCH32_REGS := 0 20ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 21$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 22endif 23 24ifeq (${TRUSTED_BOARD_BOOT}, 1) 25$(error "TRUSTED_BOARD_BOOT must be disabled") 26endif 27 28PRELOADED_BL33_BASE := 0x80080000 29 30FPGA_PRELOADED_DTB_BASE := 0x80070000 31$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) 32 33FPGA_PRELOADED_CMD_LINE := 0x1000 34$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) 35 36ENABLE_FEAT_AMU := 2 37 38# Treating this as a memory-constrained port for now 39USE_COHERENT_MEM := 0 40 41# This can be overridden depending on CPU(s) used in the FPGA image 42HW_ASSISTED_COHERENCY := 1 43 44PL011_GENERIC_UART := 1 45 46SUPPORT_UNKNOWN_MPID ?= 1 47 48FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 49 50# select a different set of CPU files, depending on whether we compile for 51# hardware assisted coherency cores or not 52ifeq (${HW_ASSISTED_COHERENCY}, 0) 53# Cores used without DSU 54 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 55 lib/cpus/aarch64/cortex_a53.S \ 56 lib/cpus/aarch64/cortex_a57.S \ 57 lib/cpus/aarch64/cortex_a72.S \ 58 lib/cpus/aarch64/cortex_a73.S 59else 60# AArch64-only cores 61 FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \ 62 lib/cpus/aarch64/cortex_a710.S \ 63 lib/cpus/aarch64/cortex_a715.S \ 64 lib/cpus/aarch64/cortex_x3.S \ 65 lib/cpus/aarch64/neoverse_n_common.S \ 66 lib/cpus/aarch64/neoverse_n1.S \ 67 lib/cpus/aarch64/neoverse_n2.S \ 68 lib/cpus/aarch64/neoverse_v1.S \ 69 lib/cpus/aarch64/cortex_hayes.S \ 70 lib/cpus/aarch64/cortex_hunter.S \ 71 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 72 lib/cpus/aarch64/cortex_chaberton.S \ 73 lib/cpus/aarch64/cortex_blackhawk.S 74 75# AArch64/AArch32 cores 76 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 77 lib/cpus/aarch64/cortex_a75.S 78endif 79 80ifeq (${SUPPORT_UNKNOWN_MPID}, 1) 81# Add support for unknown/invalid MPIDs (aarch64 only) 82$(eval $(call add_define,SUPPORT_UNKNOWN_MPID)) 83 FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S 84endif 85 86# Allow detection of GIC-600 87GICV3_SUPPORT_GIC600 := 1 88 89GIC_ENABLE_V4_EXTN := 1 90 91# Include GICv3 driver files 92include drivers/arm/gic/v3/gicv3.mk 93 94FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ 95 plat/common/plat_gicv3.c \ 96 plat/arm/board/arm_fpga/fpga_gicv3.c 97 98FDT_SOURCES := fdts/arm_fpga.dts 99 100PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include 101 102PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S 103 104BL31_SOURCES += common/fdt_fixup.c \ 105 drivers/delay_timer/delay_timer.c \ 106 drivers/delay_timer/generic_delay_timer.c \ 107 drivers/arm/pl011/${ARCH}/pl011_console.S \ 108 plat/common/plat_psci_common.c \ 109 plat/arm/board/arm_fpga/fpga_pm.c \ 110 plat/arm/board/arm_fpga/fpga_topology.c \ 111 plat/arm/board/arm_fpga/fpga_console.c \ 112 plat/arm/board/arm_fpga/fpga_bl31_setup.c \ 113 ${FPGA_CPU_LIBS} \ 114 ${FPGA_GIC_SOURCES} 115 116BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 117 118$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,bl31)) 119$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/kernel_trampoline.S,bl31)) 120$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31)) 121 122bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld 123 $(ECHO) " LD $@" 124 $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -s -n -o ${BUILD_PLAT}/bl31.axf 125 126all: bl31.axf 127