1# 2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/libfdt/libfdt.mk 8 9RESET_TO_BL31 := 1 10ifeq (${RESET_TO_BL31}, 0) 11$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") 12endif 13 14ifeq (${ENABLE_PIE}, 1) 15override SEPARATE_CODE_AND_RODATA := 1 16endif 17 18CTX_INCLUDE_AARCH32_REGS := 0 19ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 20$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 21endif 22 23ifeq (${TRUSTED_BOARD_BOOT}, 1) 24$(error "TRUSTED_BOARD_BOOT must be disabled") 25endif 26 27PRELOADED_BL33_BASE := 0x80080000 28 29FPGA_PRELOADED_DTB_BASE := 0x80070000 30$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) 31 32# Treating this as a memory-constrained port for now 33USE_COHERENT_MEM := 0 34 35# This can be overridden depending on CPU(s) used in the FPGA image 36HW_ASSISTED_COHERENCY := 1 37 38PL011_GENERIC_UART := 1 39 40FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 41 42# select a different set of CPU files, depending on whether we compile for 43# hardware assisted coherency cores or not 44ifeq (${HW_ASSISTED_COHERENCY}, 0) 45# Cores used without DSU 46 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 47 lib/cpus/aarch64/cortex_a53.S \ 48 lib/cpus/aarch64/cortex_a57.S \ 49 lib/cpus/aarch64/cortex_a72.S \ 50 lib/cpus/aarch64/cortex_a73.S 51else 52# AArch64-only cores 53 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 54 lib/cpus/aarch64/cortex_a76ae.S \ 55 lib/cpus/aarch64/cortex_a77.S \ 56 lib/cpus/aarch64/cortex_a78.S \ 57 lib/cpus/aarch64/neoverse_n1.S \ 58 lib/cpus/aarch64/neoverse_e1.S \ 59 lib/cpus/aarch64/neoverse_zeus.S \ 60 lib/cpus/aarch64/cortex_hercules_ae.S \ 61 lib/cpus/aarch64/cortex_a65.S \ 62 lib/cpus/aarch64/cortex_a65ae.S \ 63 lib/cpus/aarch64/cortex_klein.S \ 64 lib/cpus/aarch64/cortex_matterhorn.S 65 66# AArch64/AArch32 cores 67 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 68 lib/cpus/aarch64/cortex_a75.S 69endif 70 71# Allow detection of GIC-600 72GICV3_SUPPORT_GIC600 := 1 73 74# Include GICv3 driver files 75include drivers/arm/gic/v3/gicv3.mk 76 77FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ 78 plat/common/plat_gicv3.c \ 79 plat/arm/board/arm_fpga/fpga_gicv3.c 80 81PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include 82 83PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S 84 85BL31_SOURCES += common/fdt_wrappers.c \ 86 drivers/delay_timer/delay_timer.c \ 87 drivers/delay_timer/generic_delay_timer.c \ 88 drivers/arm/pl011/${ARCH}/pl011_console.S \ 89 plat/common/plat_psci_common.c \ 90 plat/arm/board/arm_fpga/fpga_pm.c \ 91 plat/arm/board/arm_fpga/fpga_topology.c \ 92 plat/arm/board/arm_fpga/fpga_console.c \ 93 plat/arm/board/arm_fpga/fpga_bl31_setup.c \ 94 ${FPGA_CPU_LIBS} \ 95 ${FPGA_GIC_SOURCES} 96 97all: bl31 98