1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 #include <platform_def.h> 13 #include "../fpga_def.h" 14 15 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16 17 #define PLATFORM_LINKER_ARCH aarch64 18 19 #define PLATFORM_STACK_SIZE UL(0x800) 20 21 #define CACHE_WRITEBACK_SHIFT U(6) 22 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 23 24 #define PLATFORM_CORE_COUNT \ 25 (FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU) 26 27 #define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) + 1 29 30 #if !ENABLE_PIE 31 #define BL31_BASE UL(0x80000000) 32 #define BL31_LIMIT UL(0x80100000) 33 #else 34 #define BL31_BASE UL(0x0) 35 #define BL31_LIMIT UL(0x01000000) 36 #endif 37 38 #define GICD_BASE 0x30000000 39 #define GICR_BASE 0x30040000 40 41 #define PLAT_SDEI_NORMAL_PRI 0x70 42 43 #define ARM_IRQ_SEC_PHY_TIMER 29 44 45 #define ARM_IRQ_SEC_SGI_0 8 46 #define ARM_IRQ_SEC_SGI_1 9 47 #define ARM_IRQ_SEC_SGI_2 10 48 #define ARM_IRQ_SEC_SGI_3 11 49 #define ARM_IRQ_SEC_SGI_4 12 50 #define ARM_IRQ_SEC_SGI_5 13 51 #define ARM_IRQ_SEC_SGI_6 14 52 #define ARM_IRQ_SEC_SGI_7 15 53 54 /* 55 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 56 * terminology. On a GICv2 system or mode, the lists will be merged and treated 57 * as Group 0 interrupts. 58 */ 59 #define PLATFORM_G1S_PROPS(grp) \ 60 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 61 GIC_INTR_CFG_LEVEL), \ 62 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 63 GIC_INTR_CFG_EDGE), \ 64 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 65 GIC_INTR_CFG_EDGE), \ 66 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 67 GIC_INTR_CFG_EDGE), \ 68 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 69 GIC_INTR_CFG_EDGE), \ 70 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 71 GIC_INTR_CFG_EDGE), \ 72 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 73 GIC_INTR_CFG_EDGE) 74 75 #define PLATFORM_G0_PROPS(grp) \ 76 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 77 GIC_INTR_CFG_EDGE), \ 78 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 79 GIC_INTR_CFG_EDGE) 80 81 #define PLAT_MAX_RET_STATE 1 82 #define PLAT_MAX_OFF_STATE 2 83 84 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 85 86 #define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 87 #define PLAT_FPGA_HOLD_STATE_WAIT 0 88 #define PLAT_FPGA_HOLD_STATE_GO 1 89 90 #define PLAT_FPGA_CONSOLE_BAUDRATE 38400 91 92 #endif 93