1*536d906aSOliver Swede /* 2*536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*536d906aSOliver Swede * 4*536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5*536d906aSOliver Swede */ 6*536d906aSOliver Swede 7*536d906aSOliver Swede #include <arch_helpers.h> 8*536d906aSOliver Swede 9*536d906aSOliver Swede #include "fpga_private.h" 10*536d906aSOliver Swede #include <platform_def.h> 11*536d906aSOliver Swede 12*536d906aSOliver Swede const unsigned char *plat_get_power_domain_tree_desc(void) 13*536d906aSOliver Swede { 14*536d906aSOliver Swede /* TODO: add description of power domain topology and PSCI implementation */ 15*536d906aSOliver Swede return NULL; 16*536d906aSOliver Swede } 17*536d906aSOliver Swede 18*536d906aSOliver Swede int plat_core_pos_by_mpidr(u_register_t mpidr) 19*536d906aSOliver Swede { 20*536d906aSOliver Swede /* 21*536d906aSOliver Swede * TODO: calculate core position in a way that accounts for CPUs that 22*536d906aSOliver Swede * potentially implement multithreading 23*536d906aSOliver Swede */ 24*536d906aSOliver Swede return (int) plat_fpga_calc_core_pos(mpidr); 25*536d906aSOliver Swede } 26