1536d906aSOliver Swede /* 2536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3536d906aSOliver Swede * 4536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5536d906aSOliver Swede */ 6536d906aSOliver Swede 7536d906aSOliver Swede #ifndef FPGA_PRIVATE_H 8536d906aSOliver Swede #define FPGA_PRIVATE_H 9536d906aSOliver Swede 10*727bbf68SJavier Almansa Sobrino #include "../fpga_def.h" 11*727bbf68SJavier Almansa Sobrino #include <platform_def.h> 12*727bbf68SJavier Almansa Sobrino 13*727bbf68SJavier Almansa Sobrino #define C_RUNTIME_READY_KEY (0xaa55aa55) 14*727bbf68SJavier Almansa Sobrino #define VALID_MPID (1U) 15*727bbf68SJavier Almansa Sobrino 16*727bbf68SJavier Almansa Sobrino #ifndef __ASSEMBLER__ 17*727bbf68SJavier Almansa Sobrino 18*727bbf68SJavier Almansa Sobrino extern unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT]; 19536d906aSOliver Swede 20536d906aSOliver Swede void fpga_console_init(void); 21536d906aSOliver Swede 2287762bceSOliver Swede void plat_fpga_gic_init(void); 2387762bceSOliver Swede void fpga_pwr_gic_on_finish(void); 2487762bceSOliver Swede void fpga_pwr_gic_off(void); 25*727bbf68SJavier Almansa Sobrino unsigned int plat_fpga_calc_core_pos(uint32_t mpid); 2687762bceSOliver Swede 27*727bbf68SJavier Almansa Sobrino #endif /* __ASSEMBLER__ */ 28*727bbf68SJavier Almansa Sobrino 29*727bbf68SJavier Almansa Sobrino #endif /* FPGA_PRIVATE_H */ 30