1536d906aSOliver Swede /* 2536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3536d906aSOliver Swede * 4536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5536d906aSOliver Swede */ 6536d906aSOliver Swede 7536d906aSOliver Swede #ifndef FPGA_PRIVATE_H 8536d906aSOliver Swede #define FPGA_PRIVATE_H 9536d906aSOliver Swede 10727bbf68SJavier Almansa Sobrino #include "../fpga_def.h" 11727bbf68SJavier Almansa Sobrino #include <platform_def.h> 12727bbf68SJavier Almansa Sobrino 13727bbf68SJavier Almansa Sobrino #define C_RUNTIME_READY_KEY (0xaa55aa55) 14727bbf68SJavier Almansa Sobrino #define VALID_MPID (1U) 15fa30f73bSAndre Przywara #define FPGA_MAX_DTB_SIZE 0x10000 16727bbf68SJavier Almansa Sobrino 17727bbf68SJavier Almansa Sobrino #ifndef __ASSEMBLER__ 18727bbf68SJavier Almansa Sobrino 19727bbf68SJavier Almansa Sobrino extern unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT]; 20536d906aSOliver Swede 21536d906aSOliver Swede void fpga_console_init(void); 22536d906aSOliver Swede 2387762bceSOliver Swede void plat_fpga_gic_init(void); 2487762bceSOliver Swede void fpga_pwr_gic_on_finish(void); 2587762bceSOliver Swede void fpga_pwr_gic_off(void); 26727bbf68SJavier Almansa Sobrino unsigned int plat_fpga_calc_core_pos(uint32_t mpid); 27283e5595SAndre Przywara unsigned int fpga_get_nr_gic_cores(void); 28c69f815bSAndre Przywara uintptr_t fpga_get_redist_size(void); 2993b785f5SAndre Przywara uintptr_t fpga_get_redist_base(void); 30*d7e39c43SAndre Przywara bool fpga_has_its(void); 3187762bceSOliver Swede 32727bbf68SJavier Almansa Sobrino #endif /* __ASSEMBLER__ */ 33727bbf68SJavier Almansa Sobrino 34727bbf68SJavier Almansa Sobrino #endif /* FPGA_PRIVATE_H */ 35