1*536d906aSOliver Swede /* 2*536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*536d906aSOliver Swede * 4*536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5*536d906aSOliver Swede */ 6*536d906aSOliver Swede 7*536d906aSOliver Swede #ifndef FPGA_PRIVATE_H 8*536d906aSOliver Swede #define FPGA_PRIVATE_H 9*536d906aSOliver Swede 10*536d906aSOliver Swede unsigned int plat_fpga_calc_core_pos(u_register_t mpidr); 11*536d906aSOliver Swede 12*536d906aSOliver Swede void fpga_console_init(void); 13*536d906aSOliver Swede 14*536d906aSOliver Swede #endif 15