1*87762bceSOliver Swede /* 2*87762bceSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*87762bceSOliver Swede * 4*87762bceSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5*87762bceSOliver Swede */ 6*87762bceSOliver Swede 7*87762bceSOliver Swede #include <drivers/arm/gicv3.h> 8*87762bceSOliver Swede #include <drivers/arm/gic_common.h> 9*87762bceSOliver Swede 10*87762bceSOliver Swede #include <plat/common/platform.h> 11*87762bceSOliver Swede #include <platform_def.h> 12*87762bceSOliver Swede 13*87762bceSOliver Swede static const interrupt_prop_t fpga_interrupt_props[] = { 14*87762bceSOliver Swede PLATFORM_G1S_PROPS(INTR_GROUP1S), 15*87762bceSOliver Swede PLATFORM_G0_PROPS(INTR_GROUP0) 16*87762bceSOliver Swede }; 17*87762bceSOliver Swede 18*87762bceSOliver Swede static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 19*87762bceSOliver Swede 20*87762bceSOliver Swede static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr) 21*87762bceSOliver Swede { 22*87762bceSOliver Swede return (unsigned int)plat_core_pos_by_mpidr(mpidr); 23*87762bceSOliver Swede } 24*87762bceSOliver Swede 25*87762bceSOliver Swede static const gicv3_driver_data_t fpga_gicv3_driver_data = { 26*87762bceSOliver Swede .gicd_base = GICD_BASE, 27*87762bceSOliver Swede .gicr_base = GICR_BASE, 28*87762bceSOliver Swede .interrupt_props = fpga_interrupt_props, 29*87762bceSOliver Swede .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props), 30*87762bceSOliver Swede .rdistif_num = PLATFORM_CORE_COUNT, 31*87762bceSOliver Swede .rdistif_base_addrs = fpga_rdistif_base_addrs, 32*87762bceSOliver Swede .mpidr_to_core_pos = fpga_mpidr_to_core_pos 33*87762bceSOliver Swede }; 34*87762bceSOliver Swede 35*87762bceSOliver Swede void plat_fpga_gic_init(void) 36*87762bceSOliver Swede { 37*87762bceSOliver Swede gicv3_driver_init(&fpga_gicv3_driver_data); 38*87762bceSOliver Swede gicv3_distif_init(); 39*87762bceSOliver Swede gicv3_rdistif_init(plat_my_core_pos()); 40*87762bceSOliver Swede gicv3_cpuif_enable(plat_my_core_pos()); 41*87762bceSOliver Swede } 42*87762bceSOliver Swede 43*87762bceSOliver Swede void fpga_pwr_gic_on_finish(void) 44*87762bceSOliver Swede { 45*87762bceSOliver Swede gicv3_rdistif_init(plat_my_core_pos()); 46*87762bceSOliver Swede gicv3_cpuif_enable(plat_my_core_pos()); 47*87762bceSOliver Swede } 48*87762bceSOliver Swede 49*87762bceSOliver Swede void fpga_pwr_gic_off(void) 50*87762bceSOliver Swede { 51*87762bceSOliver Swede gicv3_cpuif_disable(plat_my_core_pos()); 52*87762bceSOliver Swede gicv3_rdistif_off(plat_my_core_pos()); 53*87762bceSOliver Swede } 54