1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/utils_def.h> 8 9 #ifndef FPGA_DEF_H 10 #define FPGA_DEF_H 11 12 /* 13 * These are set to large values to account for images describing systems with 14 * larger cluster configurations. 15 * 16 * For cases where the number of clusters, cores or threads is smaller than a 17 * maximum value below, this does not affect the PSCI functionality as any PEs 18 * that are present will still be indexed appropriately regardless of any empty 19 * entries in the array used to represent the topology. 20 */ 21 #define FPGA_MAX_CLUSTER_COUNT 2 22 #define FPGA_MAX_CPUS_PER_CLUSTER 8 23 #define FPGA_MAX_PE_PER_CPU 4 24 25 #define FPGA_PRIMARY_CPU 0x0 26 27 /******************************************************************************* 28 * FPGA image memory map related constants 29 ******************************************************************************/ 30 31 /* UART base address and clock frequency, as configured by the image */ 32 #define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 33 #define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 34 35 #define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE 36 #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ 37 38 #define FPGA_TIMER_FREQUENCY 10000000 39 #define FPGA_TIMER_BASE 0x2a830000 40 41 #endif 42