1536d906aSOliver Swede /* 2536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3536d906aSOliver Swede * 4536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5536d906aSOliver Swede */ 6536d906aSOliver Swede 7536d906aSOliver Swede #include <lib/utils_def.h> 8536d906aSOliver Swede 9536d906aSOliver Swede #ifndef FPGA_DEF_H 10536d906aSOliver Swede #define FPGA_DEF_H 11536d906aSOliver Swede 12536d906aSOliver Swede /* 13*e726c758SOliver Swede * These are set to large values to account for images describing systems with 14*e726c758SOliver Swede * larger cluster configurations. 15*e726c758SOliver Swede * 16*e726c758SOliver Swede * For cases where the number of clusters, cores or threads is smaller than a 17*e726c758SOliver Swede * maximum value below, this does not affect the PSCI functionality as any PEs 18*e726c758SOliver Swede * that are present will still be indexed appropriately regardless of any empty 19*e726c758SOliver Swede * entries in the array used to represent the topology. 20536d906aSOliver Swede */ 21536d906aSOliver Swede #define FPGA_MAX_CLUSTER_COUNT 2 22*e726c758SOliver Swede #define FPGA_MAX_CPUS_PER_CLUSTER 8 23*e726c758SOliver Swede #define FPGA_MAX_PE_PER_CPU 4 24536d906aSOliver Swede 25536d906aSOliver Swede #define FPGA_PRIMARY_CPU 0x0 26536d906aSOliver Swede 27536d906aSOliver Swede /******************************************************************************* 28536d906aSOliver Swede * FPGA image memory map related constants 29536d906aSOliver Swede ******************************************************************************/ 30536d906aSOliver Swede 31536d906aSOliver Swede /* UART base address and clock frequency, as configured by the image */ 32536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 33536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 34536d906aSOliver Swede 35536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE 36536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ 37536d906aSOliver Swede 382d696d18SOliver Swede #define FPGA_TIMER_FREQUENCY 10000000 392d696d18SOliver Swede #define FPGA_TIMER_BASE 0x2a830000 402d696d18SOliver Swede 41536d906aSOliver Swede #endif 42