xref: /rk3399_ARM-atf/plat/arm/board/arm_fpga/fpga_def.h (revision dee3042cd6cfcd7b6995260a944d741bb93adce0)
1536d906aSOliver Swede /*
2536d906aSOliver Swede  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3536d906aSOliver Swede  *
4536d906aSOliver Swede  * SPDX-License-Identifier: BSD-3-Clause
5536d906aSOliver Swede  */
6536d906aSOliver Swede 
7536d906aSOliver Swede #include <lib/utils_def.h>
8536d906aSOliver Swede 
9536d906aSOliver Swede #ifndef FPGA_DEF_H
10536d906aSOliver Swede #define FPGA_DEF_H
11536d906aSOliver Swede 
12536d906aSOliver Swede /*
13e726c758SOliver Swede  * These are set to large values to account for images describing systems with
14e726c758SOliver Swede  * larger cluster configurations.
15e726c758SOliver Swede  *
16e726c758SOliver Swede  * For cases where the number of clusters, cores or threads is smaller than a
17e726c758SOliver Swede  * maximum value below, this does not affect the PSCI functionality as any PEs
18e726c758SOliver Swede  * that are present will still be indexed appropriately regardless of any empty
19e726c758SOliver Swede  * entries in the array used to represent the topology.
20536d906aSOliver Swede  */
21536d906aSOliver Swede #define FPGA_MAX_CLUSTER_COUNT			2
22e726c758SOliver Swede #define FPGA_MAX_CPUS_PER_CLUSTER		8
23e726c758SOliver Swede #define FPGA_MAX_PE_PER_CPU			4
24536d906aSOliver Swede 
25536d906aSOliver Swede #define FPGA_PRIMARY_CPU			0x0
26536d906aSOliver Swede /*******************************************************************************
27536d906aSOliver Swede  * FPGA image memory map related constants
28536d906aSOliver Swede  ******************************************************************************/
29536d906aSOliver Swede 
30*dee3042cSAndre Przywara /*
31*dee3042cSAndre Przywara  * UART base address, just for the crash console, as a fallback.
32*dee3042cSAndre Przywara  * The actual console UART address is taken from the DT.
33*dee3042cSAndre Przywara  */
34*dee3042cSAndre Przywara #define PLAT_FPGA_CRASH_UART_BASE		0x7ff80000
35536d906aSOliver Swede 
36670c66afSAndre Przywara #define FPGA_DEFAULT_TIMER_FREQUENCY		10000000
372d696d18SOliver Swede 
38536d906aSOliver Swede #endif
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