1*536d906aSOliver Swede /* 2*536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*536d906aSOliver Swede * 4*536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5*536d906aSOliver Swede */ 6*536d906aSOliver Swede 7*536d906aSOliver Swede #include <lib/utils_def.h> 8*536d906aSOliver Swede 9*536d906aSOliver Swede #ifndef FPGA_DEF_H 10*536d906aSOliver Swede #define FPGA_DEF_H 11*536d906aSOliver Swede 12*536d906aSOliver Swede /* 13*536d906aSOliver Swede * The initial FPGA image configures a system with 2 clusters, 1 core in each, 14*536d906aSOliver Swede * and multi-threading is unimplemented. 15*536d906aSOliver Swede */ 16*536d906aSOliver Swede #define FPGA_MAX_CLUSTER_COUNT 2 17*536d906aSOliver Swede #define FPGA_MAX_CPUS_PER_CLUSTER 1 18*536d906aSOliver Swede #define FPGA_MAX_PE_PER_CPU 1 19*536d906aSOliver Swede 20*536d906aSOliver Swede #define FPGA_PRIMARY_CPU 0x0 21*536d906aSOliver Swede 22*536d906aSOliver Swede /******************************************************************************* 23*536d906aSOliver Swede * FPGA image memory map related constants 24*536d906aSOliver Swede ******************************************************************************/ 25*536d906aSOliver Swede 26*536d906aSOliver Swede /* UART base address and clock frequency, as configured by the image */ 27*536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 28*536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 29*536d906aSOliver Swede 30*536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE 31*536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ 32*536d906aSOliver Swede 33*536d906aSOliver Swede #endif 34