1536d906aSOliver Swede /* 2536d906aSOliver Swede * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3536d906aSOliver Swede * 4536d906aSOliver Swede * SPDX-License-Identifier: BSD-3-Clause 5536d906aSOliver Swede */ 6536d906aSOliver Swede 7536d906aSOliver Swede #include <lib/utils_def.h> 8536d906aSOliver Swede 9536d906aSOliver Swede #ifndef FPGA_DEF_H 10536d906aSOliver Swede #define FPGA_DEF_H 11536d906aSOliver Swede 12536d906aSOliver Swede /* 13536d906aSOliver Swede * The initial FPGA image configures a system with 2 clusters, 1 core in each, 14536d906aSOliver Swede * and multi-threading is unimplemented. 15536d906aSOliver Swede */ 16536d906aSOliver Swede #define FPGA_MAX_CLUSTER_COUNT 2 17536d906aSOliver Swede #define FPGA_MAX_CPUS_PER_CLUSTER 1 18536d906aSOliver Swede #define FPGA_MAX_PE_PER_CPU 1 19536d906aSOliver Swede 20536d906aSOliver Swede #define FPGA_PRIMARY_CPU 0x0 21536d906aSOliver Swede 22536d906aSOliver Swede /******************************************************************************* 23536d906aSOliver Swede * FPGA image memory map related constants 24536d906aSOliver Swede ******************************************************************************/ 25536d906aSOliver Swede 26536d906aSOliver Swede /* UART base address and clock frequency, as configured by the image */ 27536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 28536d906aSOliver Swede #define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 29536d906aSOliver Swede 30536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE 31536d906aSOliver Swede #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ 32536d906aSOliver Swede 33*2d696d18SOliver Swede #define FPGA_TIMER_FREQUENCY 10000000 34*2d696d18SOliver Swede #define FPGA_TIMER_BASE 0x2a830000 35*2d696d18SOliver Swede 36536d906aSOliver Swede #endif 37