1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/fdt_wrappers.h> 10 #include <drivers/generic_delay_timer.h> 11 #include <lib/mmio.h> 12 #include <libfdt.h> 13 14 #include <plat/common/platform.h> 15 #include <platform_def.h> 16 17 #include "fpga_private.h" 18 19 static entry_point_info_t bl33_image_ep_info; 20 21 uintptr_t plat_get_ns_image_entrypoint(void) 22 { 23 #ifdef PRELOADED_BL33_BASE 24 return PRELOADED_BL33_BASE; 25 #else 26 return 0; 27 #endif 28 } 29 30 uint32_t fpga_get_spsr_for_bl33_entry(void) 31 { 32 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 33 } 34 35 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 36 u_register_t arg2, u_register_t arg3) 37 { 38 fpga_console_init(); 39 40 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 41 bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry(); 42 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 43 44 /* Set x0-x3 for the primary CPU as expected by the kernel */ 45 bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE; 46 bl33_image_ep_info.args.arg1 = 0U; 47 bl33_image_ep_info.args.arg2 = 0U; 48 bl33_image_ep_info.args.arg3 = 0U; 49 } 50 51 void bl31_plat_arch_setup(void) 52 { 53 } 54 55 void bl31_platform_setup(void) 56 { 57 /* Initialize the GIC driver, cpu and distributor interfaces */ 58 plat_fpga_gic_init(); 59 60 /* Write frequency to CNTCRL and initialize timer */ 61 generic_delay_timer_init(); 62 } 63 64 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 65 { 66 entry_point_info_t *next_image_info; 67 next_image_info = &bl33_image_ep_info; 68 69 /* Only expecting BL33: the kernel will run in EL2NS */ 70 assert(type == NON_SECURE); 71 72 /* None of the images can have 0x0 as the entrypoint */ 73 if (next_image_info->pc) { 74 return next_image_info; 75 } else { 76 return NULL; 77 } 78 } 79 80 unsigned int plat_get_syscnt_freq2(void) 81 { 82 const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE; 83 int node; 84 85 node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer"); 86 if (node < 0) { 87 return FPGA_DEFAULT_TIMER_FREQUENCY; 88 } 89 90 return fdt_read_uint32_default(fdt, node, "clock-frequency", 91 FPGA_DEFAULT_TIMER_FREQUENCY); 92 } 93 94 void bl31_plat_enable_mmu(uint32_t flags) 95 { 96 /* TODO: determine if MMU needs to be enabled */ 97 } 98