1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <lib/mmio.h> 9 #include <drivers/generic_delay_timer.h> 10 11 #include <plat/common/platform.h> 12 #include <platform_def.h> 13 14 #include "fpga_private.h" 15 16 static entry_point_info_t bl33_image_ep_info; 17 18 uintptr_t plat_get_ns_image_entrypoint(void) 19 { 20 #ifdef PRELOADED_BL33_BASE 21 return PRELOADED_BL33_BASE; 22 #else 23 return 0; 24 #endif 25 } 26 27 uint32_t fpga_get_spsr_for_bl33_entry(void) 28 { 29 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 30 } 31 32 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 33 u_register_t arg2, u_register_t arg3) 34 { 35 fpga_console_init(); 36 37 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 38 bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry(); 39 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 40 41 /* Set x0-x3 for the primary CPU as expected by the kernel */ 42 bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE; 43 bl33_image_ep_info.args.arg1 = 0U; 44 bl33_image_ep_info.args.arg2 = 0U; 45 bl33_image_ep_info.args.arg3 = 0U; 46 } 47 48 void bl31_plat_arch_setup(void) 49 { 50 } 51 52 void bl31_platform_setup(void) 53 { 54 /* Initialize the GIC driver, cpu and distributor interfaces */ 55 plat_fpga_gic_init(); 56 57 /* Write frequency to CNTCRL and initialize timer */ 58 generic_delay_timer_init(); 59 mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL)); 60 } 61 62 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 63 { 64 entry_point_info_t *next_image_info; 65 next_image_info = &bl33_image_ep_info; 66 67 /* Only expecting BL33: the kernel will run in EL2NS */ 68 assert(type == NON_SECURE); 69 70 /* None of the images can have 0x0 as the entrypoint */ 71 if (next_image_info->pc) { 72 return next_image_info; 73 } else { 74 return NULL; 75 } 76 } 77 78 unsigned int plat_get_syscnt_freq2(void) 79 { 80 return FPGA_TIMER_FREQUENCY; 81 } 82 83 void bl31_plat_enable_mmu(uint32_t flags) 84 { 85 /* TODO: determine if MMU needs to be enabled */ 86 } 87