1 /* 2 * Copyright (c) 2019-2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/smccc_def.h> 15 #include <plat/common/common_def.h> 16 17 /* Memory location options for TSP */ 18 #define ARM_DRAM_ID 2 19 20 #define ARM_DRAM1_BASE UL(0x80000000) 21 #define ARM_DRAM1_SIZE UL(0x80000000) 22 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 23 ARM_DRAM1_SIZE - 1) 24 25 #define SRAM_BASE 0x2000000 26 #define SRAM_SIZE 0x200000 27 28 /* The first 4KB of NS DRAM1 are used as shared memory */ 29 #define A5DS_SHARED_RAM_BASE SRAM_BASE 30 #define A5DS_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 31 32 /* The next 252 kB of NS DRAM is used to load the BL images */ 33 #define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \ 34 A5DS_SHARED_RAM_SIZE) 35 #define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ 36 A5DS_SHARED_RAM_SIZE) 37 38 #define PERIPHBASE 0x1a000000 39 #define PERIPH_SIZE 0x00240000 40 #define A5_PERIPHERALS_BASE 0x1c000000 41 #define A5_PERIPHERALS_SIZE 0x10000 42 43 #define ARM_CACHE_WRITEBACK_SHIFT 5 44 45 #define ARM_IRQ_SEC_PHY_TIMER 29 46 47 #define ARM_IRQ_SEC_SGI_0 8 48 #define ARM_IRQ_SEC_SGI_1 9 49 #define ARM_IRQ_SEC_SGI_2 10 50 #define ARM_IRQ_SEC_SGI_3 11 51 #define ARM_IRQ_SEC_SGI_4 12 52 #define ARM_IRQ_SEC_SGI_5 13 53 #define ARM_IRQ_SEC_SGI_6 14 54 #define ARM_IRQ_SEC_SGI_7 15 55 56 /* 57 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 58 * terminology. On a GICv2 system or mode, the lists will be merged and treated 59 * as Group 0 interrupts. 60 */ 61 #define ARM_G1S_IRQ_PROPS(grp) \ 62 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 63 GIC_INTR_CFG_LEVEL), \ 64 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 65 GIC_INTR_CFG_EDGE), \ 66 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 67 GIC_INTR_CFG_EDGE), \ 68 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 69 GIC_INTR_CFG_EDGE), \ 70 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 71 GIC_INTR_CFG_EDGE), \ 72 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 73 GIC_INTR_CFG_EDGE), \ 74 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 75 GIC_INTR_CFG_EDGE) 76 77 #define ARM_G0_IRQ_PROPS(grp) \ 78 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 79 GIC_INTR_CFG_EDGE) 80 81 #define A5DS_IRQ_TZ_WDOG 56 82 #define A5DS_IRQ_SEC_SYS_TIMER 57 83 84 /* Default cluster count for A5DS */ 85 #define A5DS_CLUSTER_COUNT U(1) 86 87 /* Default number of CPUs per cluster on A5DS */ 88 #define A5DS_MAX_CPUS_PER_CLUSTER U(4) 89 90 /* Default number of threads per CPU on A5DS */ 91 #define A5DS_MAX_PE_PER_CPU U(1) 92 93 #define A5DS_CORE_COUNT U(4) 94 95 #define A5DS_PRIMARY_CPU 0x0 96 97 #define BOOT_BASE ARM_DRAM1_BASE 98 #define BOOT_SIZE UL(0x2800000) 99 100 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE) 101 /* 102 * The last 2MB is meant to be NOLOAD and will not be zero 103 * initialized. 104 */ 105 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 106 BOOT_SIZE - \ 107 0x00200000) 108 109 #define MAP_BOOT_RW MAP_REGION_FLAT( \ 110 BOOT_BASE, \ 111 BOOT_SIZE, \ 112 MT_DEVICE | MT_RW | MT_SECURE) 113 114 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 115 A5DS_SHARED_RAM_BASE, \ 116 A5DS_SHARED_RAM_SIZE, \ 117 MT_MEMORY | MT_RW | MT_SECURE) 118 119 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 120 ARM_NS_DRAM1_BASE, \ 121 ARM_NS_DRAM1_SIZE, \ 122 MT_MEMORY | MT_RW | MT_NS) 123 124 #define ARM_MAP_SRAM MAP_REGION_FLAT( \ 125 SRAM_BASE, \ 126 SRAM_SIZE, \ 127 MT_MEMORY | MT_RW | MT_NS) 128 129 /* 130 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 131 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 132 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 133 * to be able to access the heap. 134 */ 135 136 #define ARM_MAP_BL_RO MAP_REGION_FLAT(\ 137 BL_CODE_BASE,\ 138 BL_CODE_END - BL_CODE_BASE,\ 139 MT_CODE | MT_SECURE),\ 140 MAP_REGION_FLAT(\ 141 BL_RO_DATA_BASE,\ 142 BL_RO_DATA_END\ 143 - BL_RO_DATA_BASE, \ 144 MT_RO_DATA | MT_SECURE) 145 146 #if USE_COHERENT_MEM 147 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT(\ 148 BL_COHERENT_RAM_BASE,\ 149 BL_COHERENT_RAM_END \ 150 - BL_COHERENT_RAM_BASE, \ 151 MT_DEVICE | MT_RW | MT_SECURE) 152 #endif 153 154 /* 155 * The max number of regions like RO(code), coherent and data required by 156 * different BL stages which need to be mapped in the MMU. 157 */ 158 #define ARM_BL_REGIONS 5 159 160 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 161 ARM_BL_REGIONS) 162 163 /* Memory mapped Generic timer interfaces */ 164 #define A5DS_TIMER_BASE_FREQUENCY UL(7500000) 165 166 #define ARM_CONSOLE_BAUDRATE 115200 167 168 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 169 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 170 171 /* 172 * This macro defines the deepest retention state possible. A higher state 173 * id will represent an invalid or a power down state. 174 */ 175 #define PLAT_MAX_RET_STATE 1 176 177 /* 178 * This macro defines the deepest power down states possible. Any state ID 179 * higher than this is invalid. 180 */ 181 #define PLAT_MAX_OFF_STATE 2 182 183 /* 184 * Some data must be aligned on the biggest cache line size in the platform. 185 * This is known only to the platform as it might have a combination of 186 * integrated and external caches. 187 */ 188 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 189 190 /* 191 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 192 * and limit. Leave enough space of BL2 meminfo. 193 */ 194 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 195 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 196 197 /******************************************************************************* 198 * BL1 specific defines. 199 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 200 * addresses. 201 ******************************************************************************/ 202 #define BL1_RO_BASE 0x00000000 203 #define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE 204 /* 205 * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. 206 */ 207 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 208 ARM_BL_RAM_SIZE - \ 209 (PLAT_ARM_MAX_BL1_RW_SIZE)) 210 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 211 (ARM_BL_RAM_SIZE)) 212 /******************************************************************************* 213 * BL2 specific defines. 214 ******************************************************************************/ 215 216 /* 217 * Put BL2 just below BL1. 218 */ 219 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) 220 #define BL2_LIMIT BL1_RW_BASE 221 222 /* Put BL32 below BL2 in NS DRAM.*/ 223 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 224 225 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 226 - PLAT_ARM_MAX_BL32_SIZE) 227 #define BL32_PROGBITS_LIMIT BL2_BASE 228 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 229 230 /* Required platform porting definitions */ 231 #define PLATFORM_CORE_COUNT A5DS_CORE_COUNT 232 #define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ 233 PLATFORM_CORE_COUNT) + U(1) 234 235 #define PLAT_MAX_PWR_LVL 2 236 237 /* 238 * Other platform porting definitions are provided by included headers 239 */ 240 241 /* 242 * Required ARM standard platform porting definitions 243 */ 244 245 #define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ 246 247 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 248 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x10000 /* 64KB */ 249 250 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 251 252 /* 253 * Load address of BL33 for this platform port 254 */ 255 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) 256 257 /* 258 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 259 * plat_arm_mmap array defined for each BL stage. 260 */ 261 #if defined(IMAGE_BL32) 262 # define PLAT_ARM_MMAP_ENTRIES 8 263 # define MAX_XLAT_TABLES 6 264 #else 265 # define PLAT_ARM_MMAP_ENTRIES 12 266 # define MAX_XLAT_TABLES 6 267 #endif 268 269 /* 270 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 271 * plus a little space for growth. 272 */ 273 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 274 275 /* 276 * A5DS_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 277 * little space for growth. 278 */ 279 #define A5DS_MAX_BL2_SIZE 0x11000 280 281 /* 282 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 283 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 284 * BL2 and BL1-RW 285 */ 286 #define PLAT_ARM_MAX_BL32_SIZE 0x3B000 287 /* 288 * Size of cacheable stacks 289 */ 290 #if defined(IMAGE_BL1) 291 # define PLATFORM_STACK_SIZE 0x440 292 #elif defined(IMAGE_BL2) 293 # define PLATFORM_STACK_SIZE 0x400 294 #elif defined(IMAGE_BL32) 295 # define PLATFORM_STACK_SIZE 0x440 296 #endif 297 298 #define MAX_IO_DEVICES 3 299 #define MAX_IO_HANDLES 4 300 301 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 302 #define PLAT_ARM_FIP_BASE BOOT_BASE 303 #define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) 304 305 #define PLAT_ARM_NVM_BASE BOOT_BASE 306 #define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) 307 308 /* 309 * PL011 related constants 310 */ 311 #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 312 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000) 313 314 #define PLAT_ARM_RUN_UART_BASE 0x1A210000 315 #define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000) 316 317 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 318 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 319 320 #define A5DS_TIMER_BASE_FREQUENCY UL(7500000) 321 322 /* System timer related constants */ 323 #define PLAT_ARM_NSTIMER_FRAME_ID 1 324 325 /* Mailbox base address */ 326 #define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE 327 #define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE) 328 #define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8) 329 #define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 330 A5DS_HOLD_ENTRY_SIZE) 331 #define A5DS_HOLD_ENTRY_SHIFT 3 332 #define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT) 333 #define A5DS_HOLD_STATE_WAIT 0 334 #define A5DS_HOLD_STATE_GO 1 335 336 /* Snoop Control Unit base address */ 337 #define A5DS_SCU_BASE 0x1C000000 338 339 /* 340 * GIC related constants to cater for GICv2 341 */ 342 #define PLAT_ARM_GICD_BASE 0x1C001000 343 #define PLAT_ARM_GICC_BASE 0x1C000100 344 345 /* 346 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 347 * terminology. On a GICv2 system or mode, the lists will be merged and treated 348 * as Group 0 interrupts. 349 */ 350 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 351 ARM_G1S_IRQ_PROPS(grp), \ 352 INTR_PROP_DESC(A5DS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 353 GIC_INTR_CFG_LEVEL), \ 354 INTR_PROP_DESC(A5DS_IRQ_SEC_SYS_TIMER,\ 355 GIC_HIGHEST_SEC_PRIORITY, (grp), \ 356 GIC_INTR_CFG_LEVEL) 357 358 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 359 360 #endif /* PLATFORM_DEF_H */ 361