xref: /rk3399_ARM-atf/plat/arm/board/a5ds/aarch32/a5ds_helpers.S (revision 00c7d5aca36833c2d0f5394f125233254cafd388)
1*00c7d5acSUsama Arif/*
2*00c7d5acSUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved.
3*00c7d5acSUsama Arif *
4*00c7d5acSUsama Arif * SPDX-License-Identifier: BSD-3-Clause
5*00c7d5acSUsama Arif */
6*00c7d5acSUsama Arif
7*00c7d5acSUsama Arif#include <arch.h>
8*00c7d5acSUsama Arif#include <asm_macros.S>
9*00c7d5acSUsama Arif#include <platform_def.h>
10*00c7d5acSUsama Arif
11*00c7d5acSUsama Arif	.globl	plat_secondary_cold_boot_setup
12*00c7d5acSUsama Arif	.globl	plat_get_my_entrypoint
13*00c7d5acSUsama Arif	.globl	plat_is_my_cpu_primary
14*00c7d5acSUsama Arif
15*00c7d5acSUsama Arif	/* --------------------------------------------------------------------
16*00c7d5acSUsama Arif	 * void plat_secondary_cold_boot_setup (void);
17*00c7d5acSUsama Arif	 *
18*00c7d5acSUsama Arif	 * For AArch32, cold-booting secondary CPUs is not yet
19*00c7d5acSUsama Arif	 * implemented and they panic.
20*00c7d5acSUsama Arif	 * --------------------------------------------------------------------
21*00c7d5acSUsama Arif	 */
22*00c7d5acSUsama Ariffunc plat_secondary_cold_boot_setup
23*00c7d5acSUsama Arifcb_panic:
24*00c7d5acSUsama Arif	wfi
25*00c7d5acSUsama Arif	b	cb_panic
26*00c7d5acSUsama Arifendfunc plat_secondary_cold_boot_setup
27*00c7d5acSUsama Arif
28*00c7d5acSUsama Arif	/* ---------------------------------------------------------------------
29*00c7d5acSUsama Arif	 * unsigned long plat_get_my_entrypoint (void);
30*00c7d5acSUsama Arif	 *
31*00c7d5acSUsama Arif	 * Main job of this routine is to distinguish between a cold and warm
32*00c7d5acSUsama Arif	 * boot.
33*00c7d5acSUsama Arif	 * ---------------------------------------------------------------------
34*00c7d5acSUsama Arif	 */
35*00c7d5acSUsama Ariffunc plat_get_my_entrypoint
36*00c7d5acSUsama Arif	/* TODO support warm boot */
37*00c7d5acSUsama Arif	/* Cold reset */
38*00c7d5acSUsama Arif	mov	r0, #0
39*00c7d5acSUsama Arif	bx	lr
40*00c7d5acSUsama Arif
41*00c7d5acSUsama Arifendfunc plat_get_my_entrypoint
42*00c7d5acSUsama Arif
43*00c7d5acSUsama Arif	/* -----------------------------------------------------
44*00c7d5acSUsama Arif	 * unsigned int plat_is_my_cpu_primary (void);
45*00c7d5acSUsama Arif	 *
46*00c7d5acSUsama Arif	 * Find out whether the current cpu is the primary
47*00c7d5acSUsama Arif	 * cpu.
48*00c7d5acSUsama Arif	 * -----------------------------------------------------
49*00c7d5acSUsama Arif	 */
50*00c7d5acSUsama Ariffunc plat_is_my_cpu_primary
51*00c7d5acSUsama Arif	ldcopr	r0, MPIDR
52*00c7d5acSUsama Arif	ldr	r1, =MPIDR_AFFINITY_MASK
53*00c7d5acSUsama Arif	and	r0, r1
54*00c7d5acSUsama Arif	cmp	r0, #0
55*00c7d5acSUsama Arif	moveq	r0, #1
56*00c7d5acSUsama Arif	movne	r0, #0
57*00c7d5acSUsama Arif	bx	lr
58*00c7d5acSUsama Arifendfunc plat_is_my_cpu_primary
59