xref: /rk3399_ARM-atf/plat/arm/board/a5ds/a5ds_topology.c (revision 7a8ef89f97720fcded620e8a18ac831281392239)
1*00c7d5acSUsama Arif /*
2*00c7d5acSUsama Arif  * Copyright (c) 2019, Arm Limited. All rights reserved.
3*00c7d5acSUsama Arif  *
4*00c7d5acSUsama Arif  * SPDX-License-Identifier: BSD-3-Clause
5*00c7d5acSUsama Arif  */
6*00c7d5acSUsama Arif 
7*00c7d5acSUsama Arif #include <platform_def.h>
8*00c7d5acSUsama Arif 
9*00c7d5acSUsama Arif /* The A5DS power domain tree descriptor */
10*00c7d5acSUsama Arif static const unsigned char a5ds_power_domain_tree_desc[] = {
11*00c7d5acSUsama Arif 	1,
12*00c7d5acSUsama Arif 	/* No of children for the root node */
13*00c7d5acSUsama Arif 	A5DS_CLUSTER_COUNT,
14*00c7d5acSUsama Arif 	/* No of children for the first cluster node */
15*00c7d5acSUsama Arif 	A5DS_CORE_COUNT,
16*00c7d5acSUsama Arif };
17*00c7d5acSUsama Arif 
18*00c7d5acSUsama Arif /*******************************************************************************
19*00c7d5acSUsama Arif  * This function returns the topology according to A5DS_CLUSTER_COUNT.
20*00c7d5acSUsama Arif  ******************************************************************************/
plat_get_power_domain_tree_desc(void)21*00c7d5acSUsama Arif const unsigned char *plat_get_power_domain_tree_desc(void)
22*00c7d5acSUsama Arif {
23*00c7d5acSUsama Arif 	return a5ds_power_domain_tree_desc;
24*00c7d5acSUsama Arif }
25*00c7d5acSUsama Arif 
26*00c7d5acSUsama Arif /*******************************************************************************
27*00c7d5acSUsama Arif  * Get core position using mpidr
28*00c7d5acSUsama Arif  ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)29*00c7d5acSUsama Arif int plat_core_pos_by_mpidr(u_register_t mpidr)
30*00c7d5acSUsama Arif {
31*00c7d5acSUsama Arif 	unsigned int cluster_id, cpu_id;
32*00c7d5acSUsama Arif 
33*00c7d5acSUsama Arif 	mpidr &= MPIDR_AFFINITY_MASK;
34*00c7d5acSUsama Arif 
35*00c7d5acSUsama Arif 	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
36*00c7d5acSUsama Arif 		return -1;
37*00c7d5acSUsama Arif 
38*00c7d5acSUsama Arif 	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
39*00c7d5acSUsama Arif 	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
40*00c7d5acSUsama Arif 
41*00c7d5acSUsama Arif 	if (cluster_id >= A5DS_CLUSTER_COUNT)
42*00c7d5acSUsama Arif 		return -1;
43*00c7d5acSUsama Arif 
44*00c7d5acSUsama Arif 	/*
45*00c7d5acSUsama Arif 	 * Validate cpu_id by checking whether it represents a CPU in
46*00c7d5acSUsama Arif 	 * one of the two clusters present on the platform.
47*00c7d5acSUsama Arif 	 */
48*00c7d5acSUsama Arif 	if (cpu_id >= A5DS_MAX_CPUS_PER_CLUSTER)
49*00c7d5acSUsama Arif 		return -1;
50*00c7d5acSUsama Arif 
51*00c7d5acSUsama Arif 	return (cpu_id + (cluster_id * 4));
52*00c7d5acSUsama Arif 
53*00c7d5acSUsama Arif }
54