100c7d5acSUsama Arif /* 200c7d5acSUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved. 300c7d5acSUsama Arif * 400c7d5acSUsama Arif * SPDX-License-Identifier: BSD-3-Clause 500c7d5acSUsama Arif */ 600c7d5acSUsama Arif 700c7d5acSUsama Arif #include <lib/psci/psci.h> 800c7d5acSUsama Arif #include <plat/arm/common/plat_arm.h> 9*ec885bacSUsama Arif #include <plat/common/platform.h> 10*ec885bacSUsama Arif #include <drivers/arm/gicv2.h> 11*ec885bacSUsama Arif 12*ec885bacSUsama Arif /******************************************************************************* 13*ec885bacSUsama Arif * Platform handler called when a power domain is about to be turned on. The 14*ec885bacSUsama Arif * mpidr determines the CPU to be turned on. 15*ec885bacSUsama Arif ******************************************************************************/ 16*ec885bacSUsama Arif static int a5ds_pwr_domain_on(u_register_t mpidr) 17*ec885bacSUsama Arif { 18*ec885bacSUsama Arif unsigned int pos = plat_core_pos_by_mpidr(mpidr); 19*ec885bacSUsama Arif uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE; 20*ec885bacSUsama Arif 21*ec885bacSUsama Arif hold_base[pos] = A5DS_HOLD_STATE_GO; 22*ec885bacSUsama Arif dsbish(); 23*ec885bacSUsama Arif sev(); 24*ec885bacSUsama Arif 25*ec885bacSUsama Arif return PSCI_E_SUCCESS; 26*ec885bacSUsama Arif } 27*ec885bacSUsama Arif 28*ec885bacSUsama Arif /******************************************************************************* 29*ec885bacSUsama Arif * Platform handler called when a power domain has just been powered on after 30*ec885bacSUsama Arif * being turned off earlier. The target_state encodes the low power state that 31*ec885bacSUsama Arif * each level has woken up from. 32*ec885bacSUsama Arif ******************************************************************************/ 33*ec885bacSUsama Arif void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state) 34*ec885bacSUsama Arif { 35*ec885bacSUsama Arif /* TODO: This setup is needed only after a cold boot*/ 36*ec885bacSUsama Arif gicv2_pcpu_distif_init(); 37*ec885bacSUsama Arif 38*ec885bacSUsama Arif /* Enable the gic cpu interface */ 39*ec885bacSUsama Arif gicv2_cpuif_enable(); 40*ec885bacSUsama Arif } 4100c7d5acSUsama Arif 4200c7d5acSUsama Arif /******************************************************************************* 4300c7d5acSUsama Arif * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard 4400c7d5acSUsama Arif * platform layer will take care of registering the handlers with PSCI. 4500c7d5acSUsama Arif ******************************************************************************/ 4600c7d5acSUsama Arif plat_psci_ops_t a5ds_psci_pm_ops = { 4700c7d5acSUsama Arif /* dummy struct */ 4800c7d5acSUsama Arif .validate_ns_entrypoint = NULL, 49*ec885bacSUsama Arif .pwr_domain_on = a5ds_pwr_domain_on, 50*ec885bacSUsama Arif .pwr_domain_on_finish = a5ds_pwr_domain_on_finish 5100c7d5acSUsama Arif }; 5200c7d5acSUsama Arif 5300c7d5acSUsama Arif int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 5400c7d5acSUsama Arif const plat_psci_ops_t **psci_ops) 5500c7d5acSUsama Arif { 56*ec885bacSUsama Arif uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE; 57*ec885bacSUsama Arif *mailbox = sec_entrypoint; 58*ec885bacSUsama Arif 5900c7d5acSUsama Arif *psci_ops = &a5ds_psci_pm_ops; 6000c7d5acSUsama Arif 6100c7d5acSUsama Arif return 0; 6200c7d5acSUsama Arif } 63