1*4a079c75SCarlo Caione /* 2*4a079c75SCarlo Caione * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*4a079c75SCarlo Caione * 4*4a079c75SCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 5*4a079c75SCarlo Caione */ 6*4a079c75SCarlo Caione 7*4a079c75SCarlo Caione #ifndef PLATFORM_DEF_H 8*4a079c75SCarlo Caione #define PLATFORM_DEF_H 9*4a079c75SCarlo Caione 10*4a079c75SCarlo Caione #include <arch.h> 11*4a079c75SCarlo Caione #include <lib/utils_def.h> 12*4a079c75SCarlo Caione 13*4a079c75SCarlo Caione #include "../gxl_def.h" 14*4a079c75SCarlo Caione 15*4a079c75SCarlo Caione #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16*4a079c75SCarlo Caione #define PLATFORM_LINKER_ARCH aarch64 17*4a079c75SCarlo Caione 18*4a079c75SCarlo Caione /* Special value used to verify platform parameters from BL2 to BL31 */ 19*4a079c75SCarlo Caione #define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 20*4a079c75SCarlo Caione 21*4a079c75SCarlo Caione #define PLATFORM_STACK_SIZE UL(0x1000) 22*4a079c75SCarlo Caione 23*4a079c75SCarlo Caione #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 24*4a079c75SCarlo Caione #define PLATFORM_CLUSTER_COUNT U(1) 25*4a079c75SCarlo Caione #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 26*4a079c75SCarlo Caione #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 27*4a079c75SCarlo Caione 28*4a079c75SCarlo Caione #define GXBB_PRIMARY_CPU U(0) 29*4a079c75SCarlo Caione 30*4a079c75SCarlo Caione #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 31*4a079c75SCarlo Caione #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 32*4a079c75SCarlo Caione PLATFORM_CORE_COUNT) 33*4a079c75SCarlo Caione 34*4a079c75SCarlo Caione #define PLAT_MAX_RET_STATE U(1) 35*4a079c75SCarlo Caione #define PLAT_MAX_OFF_STATE U(2) 36*4a079c75SCarlo Caione 37*4a079c75SCarlo Caione /* Local power state for power domains in Run state. */ 38*4a079c75SCarlo Caione #define PLAT_LOCAL_STATE_RUN U(0) 39*4a079c75SCarlo Caione /* Local power state for retention. Valid only for CPU power domains */ 40*4a079c75SCarlo Caione #define PLAT_LOCAL_STATE_RET U(1) 41*4a079c75SCarlo Caione /* Local power state for power-down. Valid for CPU and cluster power domains. */ 42*4a079c75SCarlo Caione #define PLAT_LOCAL_STATE_OFF U(2) 43*4a079c75SCarlo Caione 44*4a079c75SCarlo Caione /* 45*4a079c75SCarlo Caione * Macros used to parse state information from State-ID if it is using the 46*4a079c75SCarlo Caione * recommended encoding for State-ID. 47*4a079c75SCarlo Caione */ 48*4a079c75SCarlo Caione #define PLAT_LOCAL_PSTATE_WIDTH U(4) 49*4a079c75SCarlo Caione #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 50*4a079c75SCarlo Caione 51*4a079c75SCarlo Caione /* 52*4a079c75SCarlo Caione * Some data must be aligned on the biggest cache line size in the platform. 53*4a079c75SCarlo Caione * This is known only to the platform as it might have a combination of 54*4a079c75SCarlo Caione * integrated and external caches. 55*4a079c75SCarlo Caione */ 56*4a079c75SCarlo Caione #define CACHE_WRITEBACK_SHIFT U(6) 57*4a079c75SCarlo Caione #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 58*4a079c75SCarlo Caione 59*4a079c75SCarlo Caione /* Memory-related defines */ 60*4a079c75SCarlo Caione #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 61*4a079c75SCarlo Caione #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 62*4a079c75SCarlo Caione 63*4a079c75SCarlo Caione #define MAX_MMAP_REGIONS 12 64*4a079c75SCarlo Caione #define MAX_XLAT_TABLES 6 65*4a079c75SCarlo Caione 66*4a079c75SCarlo Caione #endif /* PLATFORM_DEF_H */ 67