1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl31/interrupt_mgmt.h> 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <common/ep_info.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <meson_console.h> 15 #include <platform_def.h> 16 #include <stdint.h> 17 18 /******************************************************************************* 19 * Platform memory map regions 20 ******************************************************************************/ 21 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ 22 AML_NSDRAM0_SIZE, \ 23 MT_MEMORY | MT_RW | MT_NS) 24 25 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ 26 AML_NSDRAM1_SIZE, \ 27 MT_MEMORY | MT_RW | MT_NS) 28 29 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ 30 AML_SEC_DEVICE0_SIZE, \ 31 MT_DEVICE | MT_RW | MT_SECURE) 32 33 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ 34 AML_SEC_DEVICE1_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ 38 AML_TZRAM_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ 42 AML_SEC_DEVICE2_SIZE, \ 43 MT_DEVICE | MT_RW | MT_SECURE) 44 45 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ 46 AML_SEC_DEVICE3_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 static const mmap_region_t gxl_mmap[] = { 50 MAP_NSDRAM0, 51 MAP_NSDRAM1, 52 MAP_SEC_DEVICE0, 53 MAP_SEC_DEVICE1, 54 MAP_TZRAM, 55 MAP_SEC_DEVICE2, 56 MAP_SEC_DEVICE3, 57 {0} 58 }; 59 60 /******************************************************************************* 61 * Per-image regions 62 ******************************************************************************/ 63 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ 64 BL31_END - BL31_BASE, \ 65 MT_MEMORY | MT_RW | MT_SECURE) 66 67 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ 68 BL_CODE_END - BL_CODE_BASE, \ 69 MT_CODE | MT_SECURE) 70 71 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ 72 BL_RO_DATA_END - BL_RO_DATA_BASE, \ 73 MT_RO_DATA | MT_SECURE) 74 75 #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ 76 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 77 MT_DEVICE | MT_RW | MT_SECURE) 78 79 /******************************************************************************* 80 * Function that sets up the translation tables. 81 ******************************************************************************/ 82 void aml_setup_page_tables(void) 83 { 84 #if IMAGE_BL31 85 const mmap_region_t gxl_bl_mmap[] = { 86 MAP_BL31, 87 MAP_BL_CODE, 88 MAP_BL_RO_DATA, 89 #if USE_COHERENT_MEM 90 MAP_BL_COHERENT, 91 #endif 92 {0} 93 }; 94 #endif 95 96 mmap_add(gxl_bl_mmap); 97 98 mmap_add(gxl_mmap); 99 100 init_xlat_tables(); 101 } 102 103 /******************************************************************************* 104 * Function that sets up the console 105 ******************************************************************************/ 106 static console_meson_t gxl_console; 107 108 void aml_console_init(void) 109 { 110 int rc = console_meson_register(AML_UART0_AO_BASE, 111 AML_UART0_AO_CLK_IN_HZ, 112 AML_UART_BAUDRATE, 113 &gxl_console); 114 if (rc == 0) { 115 /* 116 * The crash console doesn't use the multi console API, it uses 117 * the core console functions directly. It is safe to call panic 118 * and let it print debug information. 119 */ 120 panic(); 121 } 122 123 console_set_scope(&gxl_console.console, 124 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 125 } 126 127 /******************************************************************************* 128 * Function that returns the system counter frequency 129 ******************************************************************************/ 130 unsigned int plat_get_syscnt_freq2(void) 131 { 132 uint32_t val; 133 134 val = mmio_read_32(AML_SYS_CPU_CFG7); 135 val &= 0xFDFFFFFF; 136 mmio_write_32(AML_SYS_CPU_CFG7, val); 137 138 val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); 139 val &= 0xFFFFFE00; 140 mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); 141 142 return AML_OSC24M_CLK_IN_HZ; 143 } 144