14a079c75SCarlo Caione /* 2f681c676SCarlo Caione * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 34a079c75SCarlo Caione * 44a079c75SCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 54a079c75SCarlo Caione */ 64a079c75SCarlo Caione 74a079c75SCarlo Caione #include <assert.h> 84a079c75SCarlo Caione #include <common/bl_common.h> 94a079c75SCarlo Caione #include <common/debug.h> 104a079c75SCarlo Caione #include <common/ep_info.h> 114a079c75SCarlo Caione #include <bl31/interrupt_mgmt.h> 124a079c75SCarlo Caione #include <meson_console.h> 134a079c75SCarlo Caione #include <lib/mmio.h> 144a079c75SCarlo Caione #include <platform_def.h> 154a079c75SCarlo Caione #include <stdint.h> 164a079c75SCarlo Caione #include <lib/xlat_tables/xlat_tables_v2.h> 174a079c75SCarlo Caione 184a079c75SCarlo Caione /******************************************************************************* 194a079c75SCarlo Caione * Platform memory map regions 204a079c75SCarlo Caione ******************************************************************************/ 21*9158854aSCarlo Caione #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \ 22*9158854aSCarlo Caione AML_NSDRAM0_SIZE, \ 234a079c75SCarlo Caione MT_MEMORY | MT_RW | MT_NS) 244a079c75SCarlo Caione 25*9158854aSCarlo Caione #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \ 26*9158854aSCarlo Caione AML_NSDRAM1_SIZE, \ 274a079c75SCarlo Caione MT_MEMORY | MT_RW | MT_NS) 284a079c75SCarlo Caione 29*9158854aSCarlo Caione #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \ 30*9158854aSCarlo Caione AML_SEC_DEVICE0_SIZE, \ 314a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 324a079c75SCarlo Caione 33*9158854aSCarlo Caione #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \ 34*9158854aSCarlo Caione AML_SEC_DEVICE1_SIZE, \ 354a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 364a079c75SCarlo Caione 37*9158854aSCarlo Caione #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \ 38*9158854aSCarlo Caione AML_TZRAM_SIZE, \ 394a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 404a079c75SCarlo Caione 41*9158854aSCarlo Caione #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \ 42*9158854aSCarlo Caione AML_SEC_DEVICE2_SIZE, \ 434a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 444a079c75SCarlo Caione 45*9158854aSCarlo Caione #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \ 46*9158854aSCarlo Caione AML_SEC_DEVICE3_SIZE, \ 474a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 484a079c75SCarlo Caione 49*9158854aSCarlo Caione static const mmap_region_t gxl_mmap[] = { 504a079c75SCarlo Caione MAP_NSDRAM0, 514a079c75SCarlo Caione MAP_NSDRAM1, 524a079c75SCarlo Caione MAP_SEC_DEVICE0, 534a079c75SCarlo Caione MAP_SEC_DEVICE1, 544a079c75SCarlo Caione MAP_TZRAM, 554a079c75SCarlo Caione MAP_SEC_DEVICE2, 564a079c75SCarlo Caione MAP_SEC_DEVICE3, 574a079c75SCarlo Caione {0} 584a079c75SCarlo Caione }; 594a079c75SCarlo Caione 604a079c75SCarlo Caione /******************************************************************************* 614a079c75SCarlo Caione * Per-image regions 624a079c75SCarlo Caione ******************************************************************************/ 634a079c75SCarlo Caione #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ 644a079c75SCarlo Caione BL31_END - BL31_BASE, \ 654a079c75SCarlo Caione MT_MEMORY | MT_RW | MT_SECURE) 664a079c75SCarlo Caione 674a079c75SCarlo Caione #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ 684a079c75SCarlo Caione BL_CODE_END - BL_CODE_BASE, \ 694a079c75SCarlo Caione MT_CODE | MT_SECURE) 704a079c75SCarlo Caione 714a079c75SCarlo Caione #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ 724a079c75SCarlo Caione BL_RO_DATA_END - BL_RO_DATA_BASE, \ 734a079c75SCarlo Caione MT_RO_DATA | MT_SECURE) 744a079c75SCarlo Caione 754a079c75SCarlo Caione #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ 764a079c75SCarlo Caione BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 774a079c75SCarlo Caione MT_DEVICE | MT_RW | MT_SECURE) 784a079c75SCarlo Caione 794a079c75SCarlo Caione /******************************************************************************* 804a079c75SCarlo Caione * Function that sets up the translation tables. 814a079c75SCarlo Caione ******************************************************************************/ 82010fdc1bSCarlo Caione void aml_setup_page_tables(void) 834a079c75SCarlo Caione { 844a079c75SCarlo Caione #if IMAGE_BL31 85*9158854aSCarlo Caione const mmap_region_t gxl_bl_mmap[] = { 864a079c75SCarlo Caione MAP_BL31, 874a079c75SCarlo Caione MAP_BL_CODE, 884a079c75SCarlo Caione MAP_BL_RO_DATA, 894a079c75SCarlo Caione #if USE_COHERENT_MEM 904a079c75SCarlo Caione MAP_BL_COHERENT, 914a079c75SCarlo Caione #endif 924a079c75SCarlo Caione {0} 934a079c75SCarlo Caione }; 944a079c75SCarlo Caione #endif 954a079c75SCarlo Caione 96*9158854aSCarlo Caione mmap_add(gxl_bl_mmap); 974a079c75SCarlo Caione 98*9158854aSCarlo Caione mmap_add(gxl_mmap); 994a079c75SCarlo Caione 1004a079c75SCarlo Caione init_xlat_tables(); 1014a079c75SCarlo Caione } 1024a079c75SCarlo Caione 1034a079c75SCarlo Caione /******************************************************************************* 1044a079c75SCarlo Caione * Function that sets up the console 1054a079c75SCarlo Caione ******************************************************************************/ 106*9158854aSCarlo Caione static console_meson_t gxl_console; 1074a079c75SCarlo Caione 108010fdc1bSCarlo Caione void aml_console_init(void) 1094a079c75SCarlo Caione { 110f681c676SCarlo Caione int rc = console_meson_register(AML_UART0_AO_BASE, 111f681c676SCarlo Caione AML_UART0_AO_CLK_IN_HZ, 112f681c676SCarlo Caione AML_UART_BAUDRATE, 113*9158854aSCarlo Caione &gxl_console); 1144a079c75SCarlo Caione if (rc == 0) { 1154a079c75SCarlo Caione /* 1164a079c75SCarlo Caione * The crash console doesn't use the multi console API, it uses 1174a079c75SCarlo Caione * the core console functions directly. It is safe to call panic 1184a079c75SCarlo Caione * and let it print debug information. 1194a079c75SCarlo Caione */ 1204a079c75SCarlo Caione panic(); 1214a079c75SCarlo Caione } 1224a079c75SCarlo Caione 123*9158854aSCarlo Caione console_set_scope(&gxl_console.console, 1244a079c75SCarlo Caione CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 1254a079c75SCarlo Caione } 1264a079c75SCarlo Caione 1274a079c75SCarlo Caione /******************************************************************************* 1284a079c75SCarlo Caione * Function that returns the system counter frequency 1294a079c75SCarlo Caione ******************************************************************************/ 1304a079c75SCarlo Caione unsigned int plat_get_syscnt_freq2(void) 1314a079c75SCarlo Caione { 1324a079c75SCarlo Caione uint32_t val; 1334a079c75SCarlo Caione 134*9158854aSCarlo Caione val = mmio_read_32(AML_SYS_CPU_CFG7); 1354a079c75SCarlo Caione val &= 0xFDFFFFFF; 136*9158854aSCarlo Caione mmio_write_32(AML_SYS_CPU_CFG7, val); 1374a079c75SCarlo Caione 138*9158854aSCarlo Caione val = mmio_read_32(AML_AO_TIMESTAMP_CNTL); 1394a079c75SCarlo Caione val &= 0xFFFFFE00; 140*9158854aSCarlo Caione mmio_write_32(AML_AO_TIMESTAMP_CNTL, val); 1414a079c75SCarlo Caione 142*9158854aSCarlo Caione return AML_OSC24M_CLK_IN_HZ; 1434a079c75SCarlo Caione } 144