xref: /rk3399_ARM-atf/plat/amlogic/gxl/gxl_common.c (revision 4a079c752beef8c2e8072b55a267d4b597b1e05b)
1*4a079c75SCarlo Caione /*
2*4a079c75SCarlo Caione  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*4a079c75SCarlo Caione  *
4*4a079c75SCarlo Caione  * SPDX-License-Identifier: BSD-3-Clause
5*4a079c75SCarlo Caione  */
6*4a079c75SCarlo Caione 
7*4a079c75SCarlo Caione #include <assert.h>
8*4a079c75SCarlo Caione #include <common/bl_common.h>
9*4a079c75SCarlo Caione #include <common/debug.h>
10*4a079c75SCarlo Caione #include <common/ep_info.h>
11*4a079c75SCarlo Caione #include <bl31/interrupt_mgmt.h>
12*4a079c75SCarlo Caione #include <meson_console.h>
13*4a079c75SCarlo Caione #include <lib/mmio.h>
14*4a079c75SCarlo Caione #include <platform_def.h>
15*4a079c75SCarlo Caione #include <stdint.h>
16*4a079c75SCarlo Caione #include <lib/xlat_tables/xlat_tables_v2.h>
17*4a079c75SCarlo Caione 
18*4a079c75SCarlo Caione /*******************************************************************************
19*4a079c75SCarlo Caione  * Platform memory map regions
20*4a079c75SCarlo Caione  ******************************************************************************/
21*4a079c75SCarlo Caione #define MAP_NSDRAM0	MAP_REGION_FLAT(GXBB_NSDRAM0_BASE,		\
22*4a079c75SCarlo Caione 					GXBB_NSDRAM0_SIZE,		\
23*4a079c75SCarlo Caione 					MT_MEMORY | MT_RW | MT_NS)
24*4a079c75SCarlo Caione 
25*4a079c75SCarlo Caione #define MAP_NSDRAM1	MAP_REGION_FLAT(GXBB_NSDRAM1_BASE,		\
26*4a079c75SCarlo Caione 					GXBB_NSDRAM1_SIZE,		\
27*4a079c75SCarlo Caione 					MT_MEMORY | MT_RW | MT_NS)
28*4a079c75SCarlo Caione 
29*4a079c75SCarlo Caione #define MAP_SEC_DEVICE0	MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE,		\
30*4a079c75SCarlo Caione 					GXBB_SEC_DEVICE0_SIZE,		\
31*4a079c75SCarlo Caione 					MT_DEVICE | MT_RW | MT_SECURE)
32*4a079c75SCarlo Caione 
33*4a079c75SCarlo Caione #define MAP_SEC_DEVICE1	MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE,		\
34*4a079c75SCarlo Caione 					GXBB_SEC_DEVICE1_SIZE,		\
35*4a079c75SCarlo Caione 					MT_DEVICE | MT_RW | MT_SECURE)
36*4a079c75SCarlo Caione 
37*4a079c75SCarlo Caione #define MAP_TZRAM	MAP_REGION_FLAT(GXBB_TZRAM_BASE,		\
38*4a079c75SCarlo Caione 					GXBB_TZRAM_SIZE,		\
39*4a079c75SCarlo Caione 					MT_DEVICE | MT_RW | MT_SECURE)
40*4a079c75SCarlo Caione 
41*4a079c75SCarlo Caione #define MAP_SEC_DEVICE2	MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE,		\
42*4a079c75SCarlo Caione 					GXBB_SEC_DEVICE2_SIZE,		\
43*4a079c75SCarlo Caione 					MT_DEVICE | MT_RW | MT_SECURE)
44*4a079c75SCarlo Caione 
45*4a079c75SCarlo Caione #define MAP_SEC_DEVICE3	MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE,		\
46*4a079c75SCarlo Caione 					GXBB_SEC_DEVICE3_SIZE,		\
47*4a079c75SCarlo Caione 					MT_DEVICE | MT_RW | MT_SECURE)
48*4a079c75SCarlo Caione 
49*4a079c75SCarlo Caione static const mmap_region_t gxbb_mmap[] = {
50*4a079c75SCarlo Caione 	MAP_NSDRAM0,
51*4a079c75SCarlo Caione 	MAP_NSDRAM1,
52*4a079c75SCarlo Caione 	MAP_SEC_DEVICE0,
53*4a079c75SCarlo Caione 	MAP_SEC_DEVICE1,
54*4a079c75SCarlo Caione 	MAP_TZRAM,
55*4a079c75SCarlo Caione 	MAP_SEC_DEVICE2,
56*4a079c75SCarlo Caione 	MAP_SEC_DEVICE3,
57*4a079c75SCarlo Caione 	{0}
58*4a079c75SCarlo Caione };
59*4a079c75SCarlo Caione 
60*4a079c75SCarlo Caione /*******************************************************************************
61*4a079c75SCarlo Caione  * Per-image regions
62*4a079c75SCarlo Caione  ******************************************************************************/
63*4a079c75SCarlo Caione #define MAP_BL31	MAP_REGION_FLAT(BL31_BASE,			\
64*4a079c75SCarlo Caione 				BL31_END - BL31_BASE,			\
65*4a079c75SCarlo Caione 				MT_MEMORY | MT_RW | MT_SECURE)
66*4a079c75SCarlo Caione 
67*4a079c75SCarlo Caione #define MAP_BL_CODE	MAP_REGION_FLAT(BL_CODE_BASE,			\
68*4a079c75SCarlo Caione 				BL_CODE_END - BL_CODE_BASE,		\
69*4a079c75SCarlo Caione 				MT_CODE | MT_SECURE)
70*4a079c75SCarlo Caione 
71*4a079c75SCarlo Caione #define MAP_BL_RO_DATA	MAP_REGION_FLAT(BL_RO_DATA_BASE,		\
72*4a079c75SCarlo Caione 				BL_RO_DATA_END - BL_RO_DATA_BASE,	\
73*4a079c75SCarlo Caione 				MT_RO_DATA | MT_SECURE)
74*4a079c75SCarlo Caione 
75*4a079c75SCarlo Caione #define MAP_BL_COHERENT	MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,		\
76*4a079c75SCarlo Caione 				BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
77*4a079c75SCarlo Caione 				MT_DEVICE | MT_RW | MT_SECURE)
78*4a079c75SCarlo Caione 
79*4a079c75SCarlo Caione /*******************************************************************************
80*4a079c75SCarlo Caione  * Function that sets up the translation tables.
81*4a079c75SCarlo Caione  ******************************************************************************/
82*4a079c75SCarlo Caione void gxbb_setup_page_tables(void)
83*4a079c75SCarlo Caione {
84*4a079c75SCarlo Caione #if IMAGE_BL31
85*4a079c75SCarlo Caione 	const mmap_region_t gxbb_bl_mmap[] = {
86*4a079c75SCarlo Caione 		MAP_BL31,
87*4a079c75SCarlo Caione 		MAP_BL_CODE,
88*4a079c75SCarlo Caione 		MAP_BL_RO_DATA,
89*4a079c75SCarlo Caione #if USE_COHERENT_MEM
90*4a079c75SCarlo Caione 		MAP_BL_COHERENT,
91*4a079c75SCarlo Caione #endif
92*4a079c75SCarlo Caione 		{0}
93*4a079c75SCarlo Caione 	};
94*4a079c75SCarlo Caione #endif
95*4a079c75SCarlo Caione 
96*4a079c75SCarlo Caione 	mmap_add(gxbb_bl_mmap);
97*4a079c75SCarlo Caione 
98*4a079c75SCarlo Caione 	mmap_add(gxbb_mmap);
99*4a079c75SCarlo Caione 
100*4a079c75SCarlo Caione 	init_xlat_tables();
101*4a079c75SCarlo Caione }
102*4a079c75SCarlo Caione 
103*4a079c75SCarlo Caione /*******************************************************************************
104*4a079c75SCarlo Caione  * Function that sets up the console
105*4a079c75SCarlo Caione  ******************************************************************************/
106*4a079c75SCarlo Caione static console_meson_t gxbb_console;
107*4a079c75SCarlo Caione 
108*4a079c75SCarlo Caione void gxbb_console_init(void)
109*4a079c75SCarlo Caione {
110*4a079c75SCarlo Caione 	int rc = console_meson_register(GXBB_UART0_AO_BASE,
111*4a079c75SCarlo Caione 					GXBB_UART0_AO_CLK_IN_HZ,
112*4a079c75SCarlo Caione 					GXBB_UART_BAUDRATE,
113*4a079c75SCarlo Caione 					&gxbb_console);
114*4a079c75SCarlo Caione 	if (rc == 0) {
115*4a079c75SCarlo Caione 		/*
116*4a079c75SCarlo Caione 		 * The crash console doesn't use the multi console API, it uses
117*4a079c75SCarlo Caione 		 * the core console functions directly. It is safe to call panic
118*4a079c75SCarlo Caione 		 * and let it print debug information.
119*4a079c75SCarlo Caione 		 */
120*4a079c75SCarlo Caione 		panic();
121*4a079c75SCarlo Caione 	}
122*4a079c75SCarlo Caione 
123*4a079c75SCarlo Caione 	console_set_scope(&gxbb_console.console,
124*4a079c75SCarlo Caione 			  CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
125*4a079c75SCarlo Caione }
126*4a079c75SCarlo Caione 
127*4a079c75SCarlo Caione /*******************************************************************************
128*4a079c75SCarlo Caione  * Function that returns the system counter frequency
129*4a079c75SCarlo Caione  ******************************************************************************/
130*4a079c75SCarlo Caione unsigned int plat_get_syscnt_freq2(void)
131*4a079c75SCarlo Caione {
132*4a079c75SCarlo Caione 	uint32_t val;
133*4a079c75SCarlo Caione 
134*4a079c75SCarlo Caione 	val = mmio_read_32(GXBB_SYS_CPU_CFG7);
135*4a079c75SCarlo Caione 	val &= 0xFDFFFFFF;
136*4a079c75SCarlo Caione 	mmio_write_32(GXBB_SYS_CPU_CFG7, val);
137*4a079c75SCarlo Caione 
138*4a079c75SCarlo Caione 	val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
139*4a079c75SCarlo Caione 	val &= 0xFFFFFE00;
140*4a079c75SCarlo Caione 	mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
141*4a079c75SCarlo Caione 
142*4a079c75SCarlo Caione 	return GXBB_OSC24M_CLK_IN_HZ;
143*4a079c75SCarlo Caione }
144