1# 2# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/xlat_tables_v2/xlat_tables.mk 8 9AML_PLAT := plat/amlogic 10AML_PLAT_SOC := ${AML_PLAT}/${PLAT} 11 12PLAT_INCLUDES := -I${AML_PLAT_SOC}/include 13 14GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 15 drivers/arm/gic/v2/gicv2_main.c \ 16 drivers/arm/gic/v2/gicv2_helpers.c \ 17 plat/common/plat_gicv2.c 18 19PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ 20 ${AML_PLAT_SOC}/gxbb_common.c \ 21 ${AML_PLAT_SOC}/gxbb_topology.c \ 22 ${XLAT_TABLES_LIB_SRCS} 23 24BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 25 plat/common/plat_psci_common.c \ 26 ${AML_PLAT_SOC}/aarch64/gxbb_helpers.S \ 27 ${AML_PLAT_SOC}/gxbb_bl31_setup.c \ 28 ${AML_PLAT_SOC}/gxbb_efuse.c \ 29 ${AML_PLAT_SOC}/gxbb_mhu.c \ 30 ${AML_PLAT_SOC}/gxbb_pm.c \ 31 ${AML_PLAT_SOC}/gxbb_scpi.c \ 32 ${AML_PLAT_SOC}/gxbb_sip_svc.c \ 33 ${AML_PLAT_SOC}/gxbb_thermal.c \ 34 ${GIC_SOURCES} 35 36# Tune compiler for Cortex-A53 37ifeq ($(notdir $(CC)),armclang) 38 TF_CFLAGS_aarch64 += -mcpu=cortex-a53 39else ifneq ($(findstring clang,$(notdir $(CC))),) 40 TF_CFLAGS_aarch64 += -mcpu=cortex-a53 41else 42 TF_CFLAGS_aarch64 += -mtune=cortex-a53 43endif 44 45# Build config flags 46# ------------------ 47 48# Enable all errata workarounds for Cortex-A53 49ERRATA_A53_826319 := 1 50ERRATA_A53_835769 := 1 51ERRATA_A53_836870 := 1 52ERRATA_A53_843419 := 1 53ERRATA_A53_855873 := 1 54 55WORKAROUND_CVE_2017_5715 := 0 56 57# Have different sections for code and rodata 58SEPARATE_CODE_AND_RODATA := 1 59 60# Use Coherent memory 61USE_COHERENT_MEM := 1 62 63# Verify build config 64# ------------------- 65 66ifneq (${RESET_TO_BL31}, 0) 67 $(error Error: ${PLAT} needs RESET_TO_BL31=0) 68endif 69 70ifeq (${ARCH},aarch32) 71 $(error Error: AArch32 not supported on ${PLAT}) 72endif 73