1*4a079c75SCarlo Caione# 2*4a079c75SCarlo Caione# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*4a079c75SCarlo Caione# 4*4a079c75SCarlo Caione# SPDX-License-Identifier: BSD-3-Clause 5*4a079c75SCarlo Caione# 6*4a079c75SCarlo Caione 7*4a079c75SCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk 8*4a079c75SCarlo Caione 9*4a079c75SCarlo CaionePLAT_INCLUDES := -Iplat/amlogic/gxbb/include 10*4a079c75SCarlo Caione 11*4a079c75SCarlo CaioneGXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 12*4a079c75SCarlo Caione drivers/arm/gic/v2/gicv2_main.c \ 13*4a079c75SCarlo Caione drivers/arm/gic/v2/gicv2_helpers.c \ 14*4a079c75SCarlo Caione plat/common/plat_gicv2.c 15*4a079c75SCarlo Caione 16*4a079c75SCarlo CaionePLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \ 17*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_common.c \ 18*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_topology.c \ 19*4a079c75SCarlo Caione ${XLAT_TABLES_LIB_SRCS} 20*4a079c75SCarlo Caione 21*4a079c75SCarlo CaioneBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 22*4a079c75SCarlo Caione plat/common/plat_psci_common.c \ 23*4a079c75SCarlo Caione plat/amlogic/gxbb/aarch64/gxbb_helpers.S \ 24*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_bl31_setup.c \ 25*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_efuse.c \ 26*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_mhu.c \ 27*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_pm.c \ 28*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_scpi.c \ 29*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_sip_svc.c \ 30*4a079c75SCarlo Caione plat/amlogic/gxbb/gxbb_thermal.c \ 31*4a079c75SCarlo Caione ${GXBB_GIC_SOURCES} 32*4a079c75SCarlo Caione 33*4a079c75SCarlo Caione# Tune compiler for Cortex-A53 34*4a079c75SCarlo Caioneifeq ($(notdir $(CC)),armclang) 35*4a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 36*4a079c75SCarlo Caioneelse ifneq ($(findstring clang,$(notdir $(CC))),) 37*4a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 38*4a079c75SCarlo Caioneelse 39*4a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mtune=cortex-a53 40*4a079c75SCarlo Caioneendif 41*4a079c75SCarlo Caione 42*4a079c75SCarlo Caione# Build config flags 43*4a079c75SCarlo Caione# ------------------ 44*4a079c75SCarlo Caione 45*4a079c75SCarlo Caione# Enable all errata workarounds for Cortex-A53 46*4a079c75SCarlo CaioneERRATA_A53_826319 := 1 47*4a079c75SCarlo CaioneERRATA_A53_835769 := 1 48*4a079c75SCarlo CaioneERRATA_A53_836870 := 1 49*4a079c75SCarlo CaioneERRATA_A53_843419 := 1 50*4a079c75SCarlo CaioneERRATA_A53_855873 := 1 51*4a079c75SCarlo Caione 52*4a079c75SCarlo CaioneWORKAROUND_CVE_2017_5715 := 0 53*4a079c75SCarlo Caione 54*4a079c75SCarlo Caione# Have different sections for code and rodata 55*4a079c75SCarlo CaioneSEPARATE_CODE_AND_RODATA := 1 56*4a079c75SCarlo Caione 57*4a079c75SCarlo Caione# Use Coherent memory 58*4a079c75SCarlo CaioneUSE_COHERENT_MEM := 1 59*4a079c75SCarlo Caione 60*4a079c75SCarlo Caione# Verify build config 61*4a079c75SCarlo Caione# ------------------- 62*4a079c75SCarlo Caione 63*4a079c75SCarlo Caioneifneq (${RESET_TO_BL31}, 0) 64*4a079c75SCarlo Caione $(error Error: gxbb needs RESET_TO_BL31=0) 65*4a079c75SCarlo Caioneendif 66*4a079c75SCarlo Caione 67*4a079c75SCarlo Caioneifeq (${ARCH},aarch32) 68*4a079c75SCarlo Caione $(error Error: AArch32 not supported on gxbb) 69*4a079c75SCarlo Caioneendif 70