xref: /rk3399_ARM-atf/plat/amlogic/gxbb/platform.mk (revision 40fac1ab4cb14bdd27e076eef48b6290d8a9d454)
14a079c75SCarlo Caione#
24a079c75SCarlo Caione# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
34a079c75SCarlo Caione#
44a079c75SCarlo Caione# SPDX-License-Identifier: BSD-3-Clause
54a079c75SCarlo Caione#
64a079c75SCarlo Caione
74a079c75SCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk
84a079c75SCarlo Caione
91b250198SCarlo CaioneAML_PLAT		:=	plat/amlogic
101b250198SCarlo CaioneAML_PLAT_SOC		:=	${AML_PLAT}/${PLAT}
11*40fac1abSCarlo CaioneAML_PLAT_COMMON		:=	${AML_PLAT}/common
124a079c75SCarlo Caione
131b250198SCarlo CaionePLAT_INCLUDES		:=	-I${AML_PLAT_SOC}/include
141b250198SCarlo Caione
151b250198SCarlo CaioneGIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c	\
164a079c75SCarlo Caione				drivers/arm/gic/v2/gicv2_main.c		\
174a079c75SCarlo Caione				drivers/arm/gic/v2/gicv2_helpers.c	\
184a079c75SCarlo Caione				plat/common/plat_gicv2.c
194a079c75SCarlo Caione
204a079c75SCarlo CaionePLAT_BL_COMMON_SOURCES	:=	drivers/amlogic/console/aarch64/meson_console.S \
211b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_common.c		\
221b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_topology.c		\
234a079c75SCarlo Caione				${XLAT_TABLES_LIB_SRCS}
244a079c75SCarlo Caione
254a079c75SCarlo CaioneBL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
264a079c75SCarlo Caione				plat/common/plat_psci_common.c		\
27*40fac1abSCarlo Caione				${AML_PLAT_COMMON}/aarch64/aml_helpers.S	\
281b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_bl31_setup.c	\
291b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_efuse.c		\
301b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_mhu.c		\
311b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_pm.c		\
321b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_scpi.c		\
331b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_sip_svc.c		\
341b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_thermal.c		\
351b250198SCarlo Caione				${GIC_SOURCES}
364a079c75SCarlo Caione
374a079c75SCarlo Caione# Tune compiler for Cortex-A53
384a079c75SCarlo Caioneifeq ($(notdir $(CC)),armclang)
394a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a53
404a079c75SCarlo Caioneelse ifneq ($(findstring clang,$(notdir $(CC))),)
414a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a53
424a079c75SCarlo Caioneelse
434a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mtune=cortex-a53
444a079c75SCarlo Caioneendif
454a079c75SCarlo Caione
464a079c75SCarlo Caione# Build config flags
474a079c75SCarlo Caione# ------------------
484a079c75SCarlo Caione
494a079c75SCarlo Caione# Enable all errata workarounds for Cortex-A53
504a079c75SCarlo CaioneERRATA_A53_826319		:= 1
514a079c75SCarlo CaioneERRATA_A53_835769		:= 1
524a079c75SCarlo CaioneERRATA_A53_836870		:= 1
534a079c75SCarlo CaioneERRATA_A53_843419		:= 1
544a079c75SCarlo CaioneERRATA_A53_855873		:= 1
554a079c75SCarlo Caione
564a079c75SCarlo CaioneWORKAROUND_CVE_2017_5715	:= 0
574a079c75SCarlo Caione
584a079c75SCarlo Caione# Have different sections for code and rodata
594a079c75SCarlo CaioneSEPARATE_CODE_AND_RODATA	:= 1
604a079c75SCarlo Caione
614a079c75SCarlo Caione# Use Coherent memory
624a079c75SCarlo CaioneUSE_COHERENT_MEM		:= 1
634a079c75SCarlo Caione
644a079c75SCarlo Caione# Verify build config
654a079c75SCarlo Caione# -------------------
664a079c75SCarlo Caione
674a079c75SCarlo Caioneifneq (${RESET_TO_BL31}, 0)
681b250198SCarlo Caione  $(error Error: ${PLAT} needs RESET_TO_BL31=0)
694a079c75SCarlo Caioneendif
704a079c75SCarlo Caione
714a079c75SCarlo Caioneifeq (${ARCH},aarch32)
721b250198SCarlo Caione  $(error Error: AArch32 not supported on ${PLAT})
734a079c75SCarlo Caioneendif
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