xref: /rk3399_ARM-atf/plat/amlogic/gxbb/platform.mk (revision 1b25019896abaf79053fa4c12c1df7029f1eb2f0)
14a079c75SCarlo Caione#
24a079c75SCarlo Caione# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
34a079c75SCarlo Caione#
44a079c75SCarlo Caione# SPDX-License-Identifier: BSD-3-Clause
54a079c75SCarlo Caione#
64a079c75SCarlo Caione
74a079c75SCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk
84a079c75SCarlo Caione
9*1b250198SCarlo CaioneAML_PLAT		:=	plat/amlogic
10*1b250198SCarlo CaioneAML_PLAT_SOC		:=	${AML_PLAT}/${PLAT}
114a079c75SCarlo Caione
12*1b250198SCarlo CaionePLAT_INCLUDES		:=	-I${AML_PLAT_SOC}/include
13*1b250198SCarlo Caione
14*1b250198SCarlo CaioneGIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c	\
154a079c75SCarlo Caione				drivers/arm/gic/v2/gicv2_main.c		\
164a079c75SCarlo Caione				drivers/arm/gic/v2/gicv2_helpers.c	\
174a079c75SCarlo Caione				plat/common/plat_gicv2.c
184a079c75SCarlo Caione
194a079c75SCarlo CaionePLAT_BL_COMMON_SOURCES	:=	drivers/amlogic/console/aarch64/meson_console.S \
20*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_common.c		\
21*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_topology.c		\
224a079c75SCarlo Caione				${XLAT_TABLES_LIB_SRCS}
234a079c75SCarlo Caione
244a079c75SCarlo CaioneBL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
254a079c75SCarlo Caione				plat/common/plat_psci_common.c		\
26*1b250198SCarlo Caione				${AML_PLAT_SOC}/aarch64/gxbb_helpers.S	\
27*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_bl31_setup.c	\
28*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_efuse.c		\
29*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_mhu.c		\
30*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_pm.c		\
31*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_scpi.c		\
32*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_sip_svc.c		\
33*1b250198SCarlo Caione				${AML_PLAT_SOC}/gxbb_thermal.c		\
34*1b250198SCarlo Caione				${GIC_SOURCES}
354a079c75SCarlo Caione
364a079c75SCarlo Caione# Tune compiler for Cortex-A53
374a079c75SCarlo Caioneifeq ($(notdir $(CC)),armclang)
384a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a53
394a079c75SCarlo Caioneelse ifneq ($(findstring clang,$(notdir $(CC))),)
404a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a53
414a079c75SCarlo Caioneelse
424a079c75SCarlo Caione    TF_CFLAGS_aarch64	+=	-mtune=cortex-a53
434a079c75SCarlo Caioneendif
444a079c75SCarlo Caione
454a079c75SCarlo Caione# Build config flags
464a079c75SCarlo Caione# ------------------
474a079c75SCarlo Caione
484a079c75SCarlo Caione# Enable all errata workarounds for Cortex-A53
494a079c75SCarlo CaioneERRATA_A53_826319		:= 1
504a079c75SCarlo CaioneERRATA_A53_835769		:= 1
514a079c75SCarlo CaioneERRATA_A53_836870		:= 1
524a079c75SCarlo CaioneERRATA_A53_843419		:= 1
534a079c75SCarlo CaioneERRATA_A53_855873		:= 1
544a079c75SCarlo Caione
554a079c75SCarlo CaioneWORKAROUND_CVE_2017_5715	:= 0
564a079c75SCarlo Caione
574a079c75SCarlo Caione# Have different sections for code and rodata
584a079c75SCarlo CaioneSEPARATE_CODE_AND_RODATA	:= 1
594a079c75SCarlo Caione
604a079c75SCarlo Caione# Use Coherent memory
614a079c75SCarlo CaioneUSE_COHERENT_MEM		:= 1
624a079c75SCarlo Caione
634a079c75SCarlo Caione# Verify build config
644a079c75SCarlo Caione# -------------------
654a079c75SCarlo Caione
664a079c75SCarlo Caioneifneq (${RESET_TO_BL31}, 0)
67*1b250198SCarlo Caione  $(error Error: ${PLAT} needs RESET_TO_BL31=0)
684a079c75SCarlo Caioneendif
694a079c75SCarlo Caione
704a079c75SCarlo Caioneifeq (${ARCH},aarch32)
71*1b250198SCarlo Caione  $(error Error: AArch32 not supported on ${PLAT})
724a079c75SCarlo Caioneendif
73