14a079c75SCarlo Caione# 2ffb77421SChris Kay# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 34a079c75SCarlo Caione# 44a079c75SCarlo Caione# SPDX-License-Identifier: BSD-3-Clause 54a079c75SCarlo Caione# 64a079c75SCarlo Caione 74a079c75SCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk 84a079c75SCarlo Caione 91b250198SCarlo CaioneAML_PLAT := plat/amlogic 101b250198SCarlo CaioneAML_PLAT_SOC := ${AML_PLAT}/${PLAT} 1140fac1abSCarlo CaioneAML_PLAT_COMMON := ${AML_PLAT}/common 124a079c75SCarlo Caione 1369b315aaSCarlo CaionePLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ 1469b315aaSCarlo Caione -I${AML_PLAT_SOC}/include \ 1569b315aaSCarlo Caione -I${AML_PLAT_COMMON}/include 161b250198SCarlo Caione 171b250198SCarlo CaioneGIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 184a079c75SCarlo Caione drivers/arm/gic/v2/gicv2_main.c \ 194a079c75SCarlo Caione drivers/arm/gic/v2/gicv2_helpers.c \ 204a079c75SCarlo Caione plat/common/plat_gicv2.c 214a079c75SCarlo Caione 224a079c75SCarlo CaioneBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 234a079c75SCarlo Caione plat/common/plat_psci_common.c \ 24fab69512SCarlo Caione drivers/amlogic/console/aarch64/meson_console.S \ 25edcadeb7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ 26edcadeb7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_pm.c \ 27edcadeb7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_common.c \ 28fab69512SCarlo Caione ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ 29d498d249SCarlo Caione ${AML_PLAT_COMMON}/aml_efuse.c \ 306f3b0dc4SCarlo Caione ${AML_PLAT_COMMON}/aml_mhu.c \ 3169b315aaSCarlo Caione ${AML_PLAT_COMMON}/aml_scpi.c \ 3235aee24eSCarlo Caione ${AML_PLAT_COMMON}/aml_sip_svc.c \ 33cd94cc40SCarlo Caione ${AML_PLAT_COMMON}/aml_thermal.c \ 34fab69512SCarlo Caione ${AML_PLAT_COMMON}/aml_topology.c \ 35a759d345SCarlo Caione ${AML_PLAT_COMMON}/aml_console.c \ 36fab69512SCarlo Caione ${XLAT_TABLES_LIB_SRCS} \ 371b250198SCarlo Caione ${GIC_SOURCES} 384a079c75SCarlo Caione 394a079c75SCarlo Caione# Tune compiler for Cortex-A53 40*8620bd0bSChris Kayifeq ($($(ARCH)-cc-id),arm-clang) 414a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 42*8620bd0bSChris Kayelse ifneq ($(filter %-clang,$($(ARCH)-cc-id)),) 434a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 444a079c75SCarlo Caioneelse 454a079c75SCarlo Caione TF_CFLAGS_aarch64 += -mtune=cortex-a53 464a079c75SCarlo Caioneendif 474a079c75SCarlo Caione 484a079c75SCarlo Caione# Build config flags 494a079c75SCarlo Caione# ------------------ 504a079c75SCarlo Caione 514a079c75SCarlo Caione# Enable all errata workarounds for Cortex-A53 524a079c75SCarlo CaioneERRATA_A53_826319 := 1 534a079c75SCarlo CaioneERRATA_A53_835769 := 1 544a079c75SCarlo CaioneERRATA_A53_836870 := 1 554a079c75SCarlo CaioneERRATA_A53_843419 := 1 564a079c75SCarlo CaioneERRATA_A53_855873 := 1 574a079c75SCarlo Caione 584a079c75SCarlo CaioneWORKAROUND_CVE_2017_5715 := 0 594a079c75SCarlo Caione 604a079c75SCarlo Caione# Have different sections for code and rodata 614a079c75SCarlo CaioneSEPARATE_CODE_AND_RODATA := 1 624a079c75SCarlo Caione 634a079c75SCarlo Caione# Use Coherent memory 644a079c75SCarlo CaioneUSE_COHERENT_MEM := 1 654a079c75SCarlo Caione 664a079c75SCarlo Caione# Verify build config 674a079c75SCarlo Caione# ------------------- 684a079c75SCarlo Caione 694a079c75SCarlo Caioneifneq (${RESET_TO_BL31}, 0) 701b250198SCarlo Caione $(error Error: ${PLAT} needs RESET_TO_BL31=0) 714a079c75SCarlo Caioneendif 724a079c75SCarlo Caione 734a079c75SCarlo Caioneifeq (${ARCH},aarch32) 741b250198SCarlo Caione $(error Error: AArch32 not supported on ${PLAT}) 754a079c75SCarlo Caioneendif 76